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Andreas Sandberg 63f1d0516d arm: Fix DMA event handling bug in the PL111 model 
The PL111 model currently maintains a list of pre-allocated
DmaDoneEvents to prevent unnecessary heap allocations. This list
effectively works like a stack where the top element is the latest
scheduled event. When an event triggers, the top pointer is moved down
the stack. This obviously breaks since events usually retire from the
bottom (events don't necessarily have to retire in order), which
triggers the following assertion:

gem5.debug: build/ARM/dev/arm/pl111.cc:460: void Pl111::fillFifo(): \
  Assertion `!dmaDoneEvent[dmaPendingNum-1].scheduled()' failed.

This changeset adds a vector listing the currently unused events. This
vector acts like a stack where the an element is popped off the stack
when a new event is needed an pushed on the stack when they trigger.
2013-01-07 13:05:37 -05:00
..
alpha sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
arm arm: Fix DMA event handling bug in the PL111 model 2013-01-07 13:05:37 -05:00
mips sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
sparc sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
x86 sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
baddev.cc SE/FS: Put platform pointers in fewer objects. 2011-10-04 02:26:03 -07:00
baddev.hh AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
BadDevice.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
copy_engine.cc sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
copy_engine.hh sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
copy_engine_defs.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
CopyEngine.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
Device.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
disk_image.cc clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
disk_image.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
DiskImage.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
dma_device.cc sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
dma_device.hh sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
etherbus.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
etherbus.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
etherdevice.cc stats: only consider a formula initialized if there is a formula 2010-06-15 01:18:36 -07:00
etherdevice.hh dev: Fix ethernet device inheritance structure 2012-11-02 11:32:01 -05:00
etherdump.cc Replace curTick global variable with accessor functions. 2011-01-07 21:50:29 -08:00
etherdump.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
etherint.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
etherint.hh Devices: Make EtherInts connect in the same way memory ports currently do. 2007-08-16 16:49:02 -04:00
etherlink.cc event: minor cleanup 2011-09-22 18:59:55 -07:00
etherlink.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
Ethernet.py dev: Fix ethernet device inheritance structure 2012-11-02 11:32:01 -05:00
etherobject.hh Devices: Make EtherInts connect in the same way memory ports currently do. 2007-08-16 16:49:02 -04:00
etherpkt.cc PacketFifo: Get slack out of the EthPacketData structure. This allows 2008-06-17 21:34:27 -07:00
etherpkt.hh types: clean up types, especially signed vs unsigned 2009-06-04 23:21:12 -07:00
ethertap.cc Fix: Address a few benign memory leaks 2012-07-09 12:35:30 -04:00
ethertap.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
i8254xGBe.cc sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
i8254xGBe.hh sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
i8254xGBe_defs.hh dev: Add missing inline declarations 2012-11-02 11:32:01 -05:00
Ide.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
ide_atareg.h gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
ide_ctrl.cc clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
ide_ctrl.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
ide_disk.cc sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
ide_disk.hh MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
ide_wdcreg.h copyright: clean up copyright blocks 2011-06-02 14:36:35 -07:00
intel_8254_timer.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
intel_8254_timer.hh sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
io_device.cc sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
io_device.hh sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
isa_fake.cc IO: Handle case where ISA Fake device is being used as a fake memory. 2011-07-10 12:56:08 -05:00
isa_fake.hh AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
mc146818.cc ARM: Add RTC device for ARM platforms. 2012-03-01 17:26:31 -06:00
mc146818.hh sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
ns_gige.cc sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
ns_gige.hh sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
ns_gige_reg.h X86: Get X86_FS to compile. 2007-09-24 17:39:56 -07:00
Pci.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
pciconfigall.cc Port: Make getAddrRanges const 2012-07-09 12:35:34 -04:00
pciconfigall.hh AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
pcidev.cc sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
pcidev.hh sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
pcireg.h style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs 2008-09-10 14:26:15 -04:00
pktfifo.cc types: clean up types, especially signed vs unsigned 2009-06-04 23:21:12 -07:00
pktfifo.hh types: clean up types, especially signed vs unsigned 2009-06-04 23:21:12 -07:00
platform.cc Includes: Don't include isa_traits.hh and use the TheISA namespace unless really needed. 2011-02-23 15:10:49 -06:00
platform.hh SE/FS: Remove System::platform and Platform::intrFrequency. 2011-09-30 00:29:07 -07:00
Platform.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
ps2.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
ps2.hh ARM: PS2 encoding fix 2012-06-05 01:23:10 -04:00
rtcreg.h X86: Turn #defines into consts. 2008-03-25 02:09:18 -04:00
SConscript DMA: Split the DMA device and IO device into seperate files 2012-05-23 09:15:45 -04:00
simple_disk.cc dev: use correct delete operation in SimpleDisk 2012-05-10 18:04:27 -05:00
simple_disk.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
SimpleDisk.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
sinic.cc sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
sinic.hh sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
sinicreg.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
terminal.cc gcc: fix unused variable warnings from GCC 4.6.1 2011-12-13 11:49:27 -08:00
terminal.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
Terminal.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
uart.cc Rename SimConsole to Terminal since it makes more sense 2008-06-17 20:29:06 -07:00
uart.hh AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
Uart.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
uart8250.cc Port: Make getAddrRanges const 2012-07-09 12:35:34 -04:00
uart8250.hh AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00