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insts
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cpu: add a condition-code register class
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2013-10-15 14:22:44 -04:00 |
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isa
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ISA: Make the decode function part of the ISA's decoder.
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2012-05-25 00:55:24 -07:00 |
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linux
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scons: Add warning for overloaded virtual functions
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2013-02-19 05:56:06 -05:00 |
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decoder.cc
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ISA,CPU: Generalize and split out the components of the decode cache.
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2012-05-26 13:45:12 -07:00 |
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decoder.hh
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x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch
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2013-01-22 00:10:10 -06:00 |
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faults.hh
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Faults: Replace calls to genMachineCheckFault with M5PanicFault.
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2011-09-27 00:24:43 -07:00 |
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interrupts.cc
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SE/FS: Build the Interrupt objects in SE mode.
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2011-10-09 00:15:50 -07:00 |
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interrupts.hh
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SE/FS: Build the Interrupt objects in SE mode.
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2011-10-09 00:15:50 -07:00 |
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isa.cc
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arch: Make the ISA class inherit from SimObject
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2013-01-07 13:05:35 -05:00 |
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isa.hh
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arch: Make all register index flattening const
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2014-01-24 15:29:30 -06:00 |
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isa_traits.hh
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ISA: generic Linux thread info support
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2012-11-02 11:32:00 -05:00 |
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kernel_stats.hh
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Power: Add a stub kernel_stats.hh.
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2011-11-13 12:40:15 -08:00 |
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locked_mem.hh
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cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.
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2014-01-24 15:29:30 -06:00 |
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microcode_rom.hh
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Make commenting on close namespace brackets consistent.
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2011-01-03 14:35:43 -08:00 |
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miscregs.hh
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Make commenting on close namespace brackets consistent.
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2011-01-03 14:35:43 -08:00 |
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mmapped_ipr.hh
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arch: Add support for m5ops using mmapped IPRs
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2013-09-30 12:20:43 +02:00 |
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pagetable.cc
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Make commenting on close namespace brackets consistent.
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2011-01-03 14:35:43 -08:00 |
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pagetable.hh
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SE/FS: Get rid of includes of config/full_system.hh.
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2011-11-18 02:20:22 -08:00 |
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PowerInterrupts.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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PowerISA.py
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arch: Make the ISA class inherit from SimObject
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2013-01-07 13:05:35 -05:00 |
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PowerTLB.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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process.cc
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MEM: Make port proxies use references rather than pointers
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2012-02-24 11:45:30 -05:00 |
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process.hh
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scons: Add warning for overloaded virtual functions
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2013-02-19 05:56:06 -05:00 |
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registers.hh
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cpu: add a condition-code register class
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2013-10-15 14:22:44 -04:00 |
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remote_gdb.hh
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Make commenting on close namespace brackets consistent.
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2011-01-03 14:35:43 -08:00 |
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SConscript
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arch: Make the ISA class inherit from SimObject
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2013-01-07 13:05:35 -05:00 |
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SConsopts
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POWER: Add support for the Power ISA
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2009-10-27 09:24:39 -07:00 |
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stacktrace.cc
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Power: Add a stubbed out stacktrace.cc
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2011-11-13 12:40:15 -08:00 |
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stacktrace.hh
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trace: reimplement the DTRACE function so it doesn't use a vector
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2011-04-15 10:44:32 -07:00 |
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tlb.cc
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arch: Create a method to finalize physical addresses
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2013-06-03 13:55:41 +02:00 |
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tlb.hh
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arch: Create a method to finalize physical addresses
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2013-06-03 13:55:41 +02:00 |
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types.hh
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clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
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2012-04-14 05:43:31 -04:00 |
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utility.cc
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cpu: add a condition-code register class
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2013-10-15 14:22:44 -04:00 |
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utility.hh
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Clock: Add a Cycles wrapper class and use where applicable
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2012-08-28 14:30:33 -04:00 |
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vtophys.cc
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Implement Ali's review feedback.
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2012-01-29 02:04:34 -08:00 |
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vtophys.hh
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Merge with main repository.
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2012-01-30 21:07:57 -08:00 |
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