3db3f83a5e
The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
69 lines
2.5 KiB
Python
69 lines
2.5 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2009 The University of Edinburgh
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Timothy M. Jones
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Import('*')
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if env['TARGET_ISA'] == 'power':
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# Workaround for bug in SCons version > 0.97d20071212
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# Scons bug id: 2006 M5 Bug id: 308
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Dir('isa/formats')
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Source('decoder.cc')
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Source('insts/branch.cc')
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Source('insts/mem.cc')
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Source('insts/integer.cc')
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Source('insts/floating.cc')
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Source('insts/condition.cc')
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Source('insts/static_inst.cc')
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Source('interrupts.cc')
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Source('linux/linux.cc')
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Source('linux/process.cc')
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Source('isa.cc')
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Source('pagetable.cc')
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Source('process.cc')
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Source('stacktrace.cc')
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Source('tlb.cc')
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Source('utility.cc')
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Source('vtophys.cc')
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SimObject('PowerInterrupts.py')
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SimObject('PowerISA.py')
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SimObject('PowerTLB.py')
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DebugFlag('Power')
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# Add in files generated by the ISA description.
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isa_desc_files = env.ISADesc('isa/main.isa')
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# Only non-header files need to be compiled.
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for f in isa_desc_files:
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if not f.path.endswith('.hh'):
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Source(f)
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