gem5/src/arch
ARM gem5 Developers 612f8f074f arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli    (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt       (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole           (AArch64 NEON, validation)
Ali Saidi            (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang         (AArch64 Linux support)
Rene De Jong         (AArch64 Linux support, performance opt.)
Matt Horsnell        (AArch64 MP, validation)
Matt Evans           (device models, code integration, validation)
Chris Adeniyi-Jones  (AArch64 syscall-emulation)
Prakash Ramrakhyani  (validation)
Dam Sunwoo           (validation)
Chander Sudanthi     (validation)
Stephan Diestelhorst (validation)
Andreas Hansson      (code integration, performance opt.)
Eric Van Hensbergen  (performance opt.)
Gabe Black
2014-01-24 15:29:34 -06:00
..
alpha arch: Make all register index flattening const 2014-01-24 15:29:30 -06:00
arm arm: Add support for ARMv8 (AArch64 & AArch32) 2014-01-24 15:29:34 -06:00
generic mem: Remove explict cast from memhelper. 2014-01-24 15:29:30 -06:00
mips arch: Make all register index flattening const 2014-01-24 15:29:30 -06:00
null cpu: add a condition-code register class 2013-10-15 14:22:44 -04:00
power arch: Make all register index flattening const 2014-01-24 15:29:30 -06:00
sparc arch: Make all register index flattening const 2014-01-24 15:29:30 -06:00
x86 arch: Make all register index flattening const 2014-01-24 15:29:30 -06:00
isa_parser.py cpu: add a condition-code register class 2013-10-15 14:22:44 -04:00
micro_asm.py scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access 2009-09-22 15:24:16 -07:00
micro_asm_test.py Add a second section to make sure the ROM is extended properly. 2007-05-31 22:21:21 +00:00
SConscript cpu: add a condition-code register class 2013-10-15 14:22:44 -04:00