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basic.isa
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ARM: Define the load instructions from outside the decoder.
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2010-06-02 12:58:01 -05:00 |
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branch.isa
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ARM: Tag appropriate instructions as IsReturn
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2011-04-04 11:42:27 -05:00 |
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data.isa
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ARM: Generate condition code setting code based on which codes are set.
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2011-05-13 17:27:02 -05:00 |
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div.isa
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CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
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2010-11-15 14:04:04 -06:00 |
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fp.isa
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ARM: Further break up condition code into NZ, C, V bits.
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2011-05-13 17:27:01 -05:00 |
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insts.isa
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ARM: Add support for M5 ops in the ARM ISA
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2010-11-08 13:58:24 -06:00 |
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ldr.isa
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ARM: Construct the predicate test register for more instruction programatically.
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2011-05-13 17:27:02 -05:00 |
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m5ops.isa
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Pseudoinst: Add an initParam pseudo inst function.
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2011-09-18 23:26:39 -07:00 |
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macromem.isa
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gcc: fix an uninitialized variable warning from G++ 4.5
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2011-05-18 11:06:23 -07:00 |
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mem.isa
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ARM: Construct the predicate test register for more instruction programatically.
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2011-05-13 17:27:02 -05:00 |
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misc.isa
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Fix bugs due to interaction between SEV instructions and O3 pipeline
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2011-08-19 15:08:07 -05:00 |
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mult.isa
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ARM: Construct the predicate test register for more instruction programatically.
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2011-05-13 17:27:02 -05:00 |
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neon.isa
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ARM: Cleanup and small fixes to some NEON ops to match the spec.
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2011-04-04 11:42:28 -05:00 |
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str.isa
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ARM: Construct the predicate test register for more instruction programatically.
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2011-05-13 17:27:02 -05:00 |
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swap.isa
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ARM: Fix SWP/SWPB undefined instruction behavior
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2011-07-15 11:53:34 -05:00 |
