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gem5/src/cpu
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Dam Sunwoo 5008a20aa4 cpu: fix bimodal predictor to use correct global history reg 
A small bug in the bimodal predictor caused significant degradation in
performance on some benchmarks. This was caused by using the wrong
globalHistoryReg during the update phase. This patches fixes the bug
and brings the performance to normal level.
2014-09-03 07:42:41 -04:00
..
checker arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
inorder arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
kvm kvm, x86: Add initial support for multicore simulation 2014-04-09 16:01:58 +02:00
minor arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
nocpu arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
o3 cpu: Fix cache blocked load behavior in o3 cpu 2014-09-03 07:42:39 -04:00
ozone arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
pred cpu: fix bimodal predictor to use correct global history reg 2014-09-03 07:42:41 -04:00
simple arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
testers mem: change the namespace Message to ProtoMessage 2014-09-01 16:55:46 -05:00
activity.cc Fix: Address a few benign memory leaks 2012-07-09 12:35:30 -04:00
activity.hh cpu: Useful getters for ActivityRecorder 2014-05-09 18:58:48 -04:00
base.cc arch, arm: Preserve TLB bootUncacheability when switching CPUs 2014-05-09 18:58:47 -04:00
base.hh cpu, arm: Allow the specification of a socket field 2014-05-09 18:58:46 -04:00
base_dyn_inst.hh arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
base_dyn_inst_impl.hh cpu: Add support for instructions that zero cache lines. 2014-01-24 15:29:30 -06:00
BaseCPU.py cpu, arm: Allow the specification of a socket field 2014-05-09 18:58:46 -04:00
CheckerCPU.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
cpuevent.cc
cpuevent.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
decode_cache.hh ISA,CPU: Generalize and split out the components of the decode cache. 2012-05-26 13:45:12 -07:00
dummy_checker.cc sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
dummy_checker.hh cpu: Add header files for checker CPUs 2012-11-02 11:32:01 -05:00
DummyChecker.py cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy 2013-02-15 17:40:08 -05:00
exec_context.cc arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
exec_context.hh arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
exetrace.cc style: eliminate equality tests with true and false 2014-05-31 18:00:23 -07:00
exetrace.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
ExeTracer.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
func_unit.cc params: Deprecate old-style constructors; update most SimObject constructors. 2007-08-30 15:16:59 -04:00
func_unit.hh Param: Transition to Cycles for relevant parameters 2012-09-07 12:34:38 -04:00
FuncUnit.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
inst_seq.hh build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
inteltrace.cc gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
inteltrace.hh sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
IntelTrace.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
intr_control.cc SE/FS: Get rid of FULL_SYSTEM in the CPU directory. 2011-11-18 01:33:28 -08:00
intr_control.hh arch: Header clean up for NOISA resurrection 2013-09-04 13:22:55 -04:00
intr_control_noisa.cc arch: Resurrect the NOISA build target and rename it NULL 2013-09-04 13:22:57 -04:00
IntrControl.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
legiontrace.cc Decoder: Remove the thread context get/set from the decoder. 2013-01-04 19:00:45 -06:00
legiontrace.hh scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
LegionTrace.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
m5legion_interface.h add fsr to the list of registers we are interested in 2007-01-30 18:27:04 -05:00
nativetrace.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
nativetrace.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
NativeTrace.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
op_class.hh CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. 2010-11-15 14:04:04 -06:00
pc_event.cc arm: Enable support for triggering a sim panic on kernel panics 2013-04-22 13:20:31 -04:00
pc_event.hh arm: Enable support for triggering a sim panic on kernel panics 2013-04-22 13:20:31 -04:00
profile.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
profile.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
quiesce_event.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
quiesce_event.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
reg_class.cc cpu: add a condition-code register class 2013-10-15 14:22:44 -04:00
reg_class.hh cpu: add a condition-code register class 2013-10-15 14:22:44 -04:00
SConscript arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
simple_thread.cc arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
simple_thread.hh arch, cpu: Add support for flattening misc register indexes. 2014-01-24 15:29:30 -06:00
smt.hh includes: fix up code after sorting 2011-04-15 10:44:14 -07:00
static_inst.cc cpu: Add flag name printing to StaticInst 2014-05-09 18:58:47 -04:00
static_inst.hh arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
static_inst_fwd.hh cpu: Don't forward declare RefCountingPtr 2014-08-13 06:57:26 -04:00
StaticInstFlags.py cpu: Add flag name printing to StaticInst 2014-05-09 18:58:47 -04:00
thread_context.cc cpu: add a condition-code register class 2013-10-15 14:22:44 -04:00
thread_context.hh cpu, arm: Allow the specification of a socket field 2014-05-09 18:58:46 -04:00
thread_state.cc mem: Set the cache line size on a system level 2013-07-18 08:31:16 -04:00
thread_state.hh cpu, arm: Allow the specification of a socket field 2014-05-09 18:58:46 -04:00
timebuf.hh cpu: Timebuf const accessors 2014-05-09 18:58:47 -04:00
timing_expr.cc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
timing_expr.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
TimingExpr.py cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
translation.hh cpu: Fix setTranslateLatency() bug for squashed instructions 2014-04-23 05:18:26 -04:00