..
insts
includes: sort all includes
2011-04-15 10:44:06 -07:00
isa
ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.
2011-07-02 22:35:04 -07:00
linux
ARM: Add support for loading the a bootloader and configuring parameters for it
2011-05-04 20:38:28 -05:00
ArmInterrupts.py
ARM: Boilerplate full-system code.
2009-11-17 18:02:08 -06:00
ArmNativeTrace.py
ARM: Make the ARM native tracer stop M5 if control diverges.
2009-07-29 00:17:11 -07:00
ArmSystem.py
ARM: Better RealView/Versatile EB platform support.
2011-05-13 17:27:00 -05:00
ArmTLB.py
ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.
2010-06-02 12:58:16 -05:00
faults.cc
O3: Fix issue with interrupts/faults occuring in the middle of a macro-op
2011-05-23 10:40:18 -05:00
faults.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
interrupts.cc
ARM: Implement ARM CPU interrupts
2010-06-02 12:58:16 -05:00
interrupts.hh
ARM: Implement WFE/WFI/SEV semantics.
2011-05-04 20:38:28 -05:00
intregs.hh
ARM: Further break up condition code into NZ, C, V bits.
2011-05-13 17:27:01 -05:00
isa.cc
ARM: Remove the saturating (Q) condition code from the renamed register.
2011-05-13 17:27:01 -05:00
isa.hh
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
isa_traits.hh
ARM: Make Noop actually decode to a noop and set it's instflags.
2011-02-23 15:10:49 -06:00
kernel_stats.hh
Make commenting on close namespace brackets consistent.
2011-01-03 14:35:43 -08:00
locked_mem.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
microcode_rom.hh
arm: include missing file for arm
2009-04-21 15:40:26 -07:00
miscregs.cc
ARM: Adds dummy support for a L2 latency miscreg.
2011-02-23 15:10:48 -06:00
miscregs.hh
ARM: Further break up condition code into NZ, C, V bits.
2011-05-13 17:27:01 -05:00
mmapped_ipr.hh
Spelling: Fix the a spelling error by changing mmaped to mmapped.
2011-03-01 23:18:47 -08:00
nativetrace.cc
ARM: Further break up condition code into NZ, C, V bits.
2011-05-13 17:27:01 -05:00
nativetrace.hh
ARM: Add vfpv3 support to native trace.
2011-05-04 20:38:26 -05:00
pagetable.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
predecoder.cc
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
predecoder.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
process.cc
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
process.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
registers.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
remote_gdb.cc
copyright: clean up copyright blocks
2011-06-02 14:36:35 -07:00
remote_gdb.hh
ARM: Add support for GDB on ARM
2010-11-15 14:04:03 -06:00
SConscript
scons: rename TraceFlags to DebugFlags
2011-06-02 17:36:21 -07:00
SConsopts
arm: add ARM support to M5
2009-04-05 18:53:15 -07:00
stacktrace.cc
sim: Use forward declarations for ports.
2010-11-08 13:58:22 -06:00
stacktrace.hh
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
system.cc
ARM: Better RealView/Versatile EB platform support.
2011-05-13 17:27:00 -05:00
system.hh
ARM: Add support for loading the a bootloader and configuring parameters for it
2011-05-04 20:38:28 -05:00
table_walker.cc
fix some build problems from prior changesets
2011-04-20 18:45:03 -07:00
table_walker.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
tlb.cc
ARM: Handle case where new TLB size is different from previous TLB size.
2011-06-16 15:08:12 -05:00
tlb.hh
ARM: Better RealView/Versatile EB platform support.
2011-05-13 17:27:00 -05:00
types.hh
cpus/isa: add a != operator for pcstate
2011-06-19 21:43:33 -04:00
utility.cc
ARM: Add support for loading the a bootloader and configuring parameters for it
2011-05-04 20:38:28 -05:00
utility.hh
ARM: Further break up condition code into NZ, C, V bits.
2011-05-13 17:27:01 -05:00
vtophys.cc
ARM: Implement functional virtual to physical address translation
2010-10-01 16:03:27 -05:00
vtophys.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00