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gem5/cpu
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Steve Reinhardt 37c860d334 Get rid of validInstAddr() & validDataAddr(). 
SE mode can now use page tables to determine which addresses are valid.

sim/process.cc:
sim/process.hh:
    Get rid of validInstAddr() & validDataAddr().
    SE mode can now use page tables to determine which addresses are valid.
    Also get rid of some Process object fields that were only used by those functions.

--HG--
extra : convert_revision : 74a25c0c2453bfc598eedacdbfccea1cf6493ba6
2006-03-12 16:01:41 -05:00
..
memtest Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
o3 Eliminated TARGET_ALPHA, since THE_ISA provides the same function. 2006-03-10 16:26:31 -05:00
ozone Cleaned up some of the Fault system. 2006-03-01 05:26:08 -05:00
simple Clean up "using" declarations. 2006-03-12 15:14:07 -05:00
trace Made Addr a global type 2006-02-21 03:38:21 -05:00
base.cc Hand merge. Stuff probably doesn't compile. 2006-03-09 18:35:28 -05:00
base.hh Hand merge. Stuff probably doesn't compile. 2006-03-09 18:35:28 -05:00
base_dyn_inst.cc Merge ktlim@zizzer:/bk/m5 2006-03-05 00:34:54 -05:00
base_dyn_inst.hh Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
cpu_exec_context.cc MIPS is back to compiling and building now! 2006-03-12 05:57:34 -05:00
cpu_exec_context.hh Get rid of validInstAddr() & validDataAddr(). 2006-03-12 16:01:41 -05:00
cpu_models.py Enable building only selected CPU models via new scons 2006-02-23 17:00:29 -05:00
exec_context.hh Get rid of validInstAddr() & validDataAddr(). 2006-03-12 16:01:41 -05:00
exetrace.cc Hand merge. Stuff probably doesn't compile. 2006-03-09 18:35:28 -05:00
exetrace.hh Made Addr a global type 2006-02-21 03:38:21 -05:00
inst_seq.hh fix problems on darwin/*BSD for syscall emulation mode 2006-02-10 14:21:32 -05:00
intr_control.cc Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
intr_control.hh Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
op_class.cc Move op_class.hh out of encumbered/cpu/full and into cpu. 2006-02-21 22:12:27 -05:00
op_class.hh Move op_class.hh out of encumbered/cpu/full and into cpu. 2006-02-21 22:12:27 -05:00
pc_event.cc Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. 2006-03-04 15:18:40 -05:00
pc_event.hh Work towards factoring isa_traits.hh into smaller, more specialized files. 2006-03-10 19:11:27 -05:00
profile.cc Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
profile.hh Updates for the quiesceEvent that was added to the XC. 2006-03-07 19:59:12 -05:00
SConscript Make sure cpu/static_inst_exec_sigs.hh get rebuilt when 2006-02-25 22:57:46 -05:00
smt.hh Many files: 2005-06-05 05:16:00 -04:00
static_inst.cc Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. 2006-02-19 02:34:37 -05:00
static_inst.hh Work towards factoring isa_traits.hh into smaller, more specialized files. 2006-03-10 19:11:27 -05:00