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Author SHA1 Message Date
Gabe Black
f410d5f4e0 Don't have "predict" set the predicted target of the instruction. Do that explicitly when you use predict. 
--HG--
extra : convert_revision : 8b613bb365b31ffaef1cea9fd789abe46219bdcf
 2006-12-16 07:39:44 -05:00
Gabe Black
569e0e883b Add in constants which let you explicitly check if endian conversion would do anything. This was needed for a case where a piece of data was within a larger data type. When the larger data type was swapped, the location of the smaller data type would move. 
--HG--
extra : convert_revision : 4c904c964678529c72b8f1044dfcb400604f6654
 2006-12-16 07:37:33 -05:00
Gabe Black
c6944e320c Add in capability to return to unblocking after a squash. This is needed because if you don't squash -all- the instructions, you need to keep clearing out whatever is left in the skid buffer. 
--HG--
extra : convert_revision : 7308eda27f4366348cf5fce71ddfa4b217bc172d
 2006-12-16 07:35:56 -05:00
Gabe Black
244506ae12 Make sure endian conversion is done on the memory data when it's just set to an existing buffer. 
--HG--
extra : convert_revision : 5a890091b6a31b5414acbf68f19e28d7122a98d7
 2006-12-16 07:34:34 -05:00
Gabe Black
6413b74e4f Make the decoder use the new setup in the dyninsts for branch prediction. 
--HG--
extra : convert_revision : 9a6d6c93e5b40a55774891df54d290ff557b322c
 2006-12-16 07:33:08 -05:00
Gabe Black
37b9966eb4 Made branch delay slots get squashed, and passed back an NPC and NNPC to start fetching from. 
--HG--
extra : convert_revision : a2e4845fedf113b5a2fd92d3d28ce5b006278103
 2006-12-16 07:32:06 -05:00
Gabe Black
4d66ddbe35 Added a predicted NPC field, explicitly stored whether the instruction was predicted taken or not. 
--HG--
extra : convert_revision : ba668af302ca4d8a3a032e907d5058e1477f462a
 2006-12-16 07:22:19 -05:00
Gabe Black
181f4f32f6 Made changes to CWP be non speculative. 
--HG--
extra : convert_revision : 43899bc97061c33e67a53179c23e46b079118117
 2006-12-16 07:10:58 -05:00
Gabe Black
6aa06a26b7 Changes to the isa_parser and affected files to fix an indexing problem with split execute instructions and miscregs aliasing with integer registers. 
src/arch/isa_parser.py:
    Rearranged things so that classes with more than one execute function treat operands properly.
    1. Eliminated the CodeBlock class
    2. Created a SubOperandList
    3. Redefined how InstObjParams is constructed

    To define an InstObjParam, you can either pass in a single code literal which will be named "code", or you can pass in a dictionary of code snippets which will be substituted into the Templates. In order to get this to work, there is a new restriction that each template has only one function in it. These changes should only affect memory instructions which have regular and split execute functions.

    Also changed the MiscRegs so that they use the instrunctions srcReg and destReg arrays.
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/branch.isa:
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa/formats/nop.isa:
src/arch/sparc/isa/formats/priv.isa:
src/arch/sparc/isa/formats/trap.isa:
    Rearranged to work with new InstObjParam scheme.
src/cpu/o3/sparc/dyn_inst.hh:
    Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. Also changed the names of the other accessors so that they have the suffix "Operand" if they use those arrays.
src/cpu/simple/base.hh:
    Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays.

--HG--
extra : convert_revision : c91e1073138b72bcf4113a721e0ed40ec600cf2e
 2006-12-16 07:10:04 -05:00
Gabe Black
90907f6b3c Merge zizzer:/bk/newmem/ 
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 17d6c49ee15af5d192dedf82871159219d4277cd
 2006-12-12 18:10:00 -05:00
Steve Reinhardt
6c8c86f2f9 Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version. 
--HG--
extra : convert_revision : b33ce0ebe2fee86cc791c00a35d8c6e395e1380c
 2006-12-12 09:58:40 -08:00
Steve Reinhardt
cdc3e5bc22 Get rid of unused lock code. 
--HG--
extra : convert_revision : a8030132268662ca54f487b8d32d09ba224317a8
 2006-12-12 02:21:03 -05:00
Kevin Lim
34924ce3b8 Fix up in case a req hasn't yet been generated for this instruction (if there was a fault prior to translation). 
--HG--
extra : convert_revision : 43f4ea5e6a234cc6071006eab72135c11b8523c8
 2006-12-11 23:51:21 -05:00
Kevin Lim
1868c9fd7f Fix for fetch to use the icache's block size to generate proper access size. 
--HG--
extra : convert_revision : 0f292233ac05b584f527c32f80e3ca3d40a6a2c1
 2006-12-11 23:47:30 -05:00
Steve Reinhardt
cfc6710f63 Merge vm1.(none):/home/stever/bk/newmem-head 
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : e1ed5c8edb95e99200b4d26317f55f71338a96df
 2006-12-09 22:05:30 -08:00
Gabe Black
498e235ae0 Fixed to take into account the misc regs that became int regs. 
--HG--
extra : convert_revision : b4f78f6e48fdd2f1774ba63b28615e0d2556b7b9
 2006-12-07 19:00:46 -05:00
Gabe Black
97cdd5198b Compilation fixes 
--HG--
extra : convert_revision : 974e91a960251a35d5ebb76c7e6c7ac330339896
 2006-12-07 18:49:10 -05:00
Gabe Black
0f8fd5fd68 Fix for squashing during a serializing instruction. 
--HG--
extra : convert_revision : 04f9131258bfb7cca1654e00273edb29bde2366b
 2006-12-07 18:47:33 -05:00
Gabe Black
41051f35ac Make branches handle the lack of a symbol table or the lack of a symbol gracefully. 
--HG--
extra : convert_revision : 7bb16405999b86f9fa082a6d44da43d346edc182
 2006-12-07 18:45:30 -05:00
Gabe Black
015873fa86 Change how Page Faults work in SPARC. It now prints the faulting address, and panics instead of fatals. This isn't technically what it should do, but it makes gdb stop at the panic rather than letting m5 exit. 
--HG--
extra : convert_revision : 3b14c99edaf649e0809977c9579afb2b7b0d72e9
 2006-12-07 18:43:55 -05:00
Kevin Lim
b618e733bd Fix for MIPS_SE/m5.fast compile. 
--HG--
extra : convert_revision : dbb893250974ac6db7b6c1ba67263fd35098ca43
 2006-12-06 14:23:31 -05:00
Gabe Black
50b8cce355 Use the renamed register index, rather than the flattened one. 
--HG--
extra : convert_revision : 599650c408667bb1b8db20a6847b9e697f7b49e4
 2006-12-06 11:40:41 -05:00
Gabe Black
f04fcf58f1 Got rid of some typedefs and moved the tlbs into the base o3 cpu. 
--HG--
extra : convert_revision : dcd1d2a64fd91aded15c8c763a78b4eebf421870
 2006-12-06 11:39:49 -05:00
Gabe Black
07a4e2cd36 Use the setSyscallReturn defined in arch rather than duplicating it here. 
--HG--
extra : convert_revision : 862ece59aa253b52b6744a0a76738d5ee19561b3
 2006-12-06 11:38:39 -05:00
Gabe Black
ef942ceecb Moved the RegIdx arrays to the base dyninst. 
--HG--
extra : convert_revision : d705cde25c2cf1add20669e99d086add49141518
 2006-12-06 11:37:39 -05:00
Gabe Black
6826ee53db Got rid of some typedefs, moved the tlbs to the base o3 cpu, and called the architecture defined setSyscallReturn function instead of a duplicate copy. 
src/cpu/o3/alpha/cpu.hh:
    Got rid of some typedefs, and moved the tlbs to the base o3 cpu.
src/cpu/o3/alpha/thread_context.hh:
src/cpu/o3/cpu.cc:
    Moved the tlbs to the base o3 cpu.

--HG--
extra : convert_revision : 1805613aa230b8974a226ee3d2584c85f7a578aa
 2006-12-06 11:36:40 -05:00
Gabe Black
0ed6c52c1e Made the alpha setSyscallReturn take a ThreadContext pointer instead of a RegFile *. 
--HG--
extra : convert_revision : 021a1fe6760df1daf6299d46060371a5310f008a
 2006-12-06 11:33:37 -05:00
Gabe Black
b3cfa6ec42 Added a flattenIntIndex function for Alpha. 
--HG--
extra : convert_revision : 5ed79ed18e443118a28d6890327c55a6a3fcd325
 2006-12-06 11:30:41 -05:00
Gabe Black
2dcf00bc8b Merge zizzer:/bk/newmem 
into  zower.eecs.umich.edu:/eecshome/m5/newmem

src/cpu/o3/commit_impl.hh:
    Hand Merge

--HG--
extra : convert_revision : 6984db90d5b5ec71c31f1c345f5a77eed540059e
 2006-12-06 06:05:28 -05:00
Gabe Black
be29adf51c Added a DPRINTF to print out the actual value pulled from memory. 
--HG--
extra : convert_revision : 18780f753a7e98f8de3047dd6781b944b0826b4e
 2006-12-06 06:02:13 -05:00
Gabe Black
75b93179ab Flattening and syscallReturn fixes 
src/cpu/o3/thread_context_impl.hh:
    Use flattened indices
src/cpu/simple_thread.hh:
    Use flattened indices, and pass a thread context to setSyscallReturn rather than a register file.
src/cpu/thread_context.hh:
    The SyscallReturn class is no longer in arch/syscallreturn.hh

--HG--
extra : convert_revision : ed84bb8ac5ef0774526ecd0d7270b0c60cd3708e
 2006-12-06 06:00:04 -05:00
Gabe Black
1886795368 Don't panic, but this needs to be fixed. 
--HG--
extra : convert_revision : 7a4aed238d437dbb2cc5946b3045d53697070a27
 2006-12-06 05:58:07 -05:00
Gabe Black
1d7d7df315 Make syscalls flatten their register indices, and also call into the ISA's setSyscallReturn function rather than having a duplicated one. 
--HG--
extra : convert_revision : 1e83ef629a7fd143f2e35e68abaa56f81d6b9d9e
 2006-12-06 05:56:34 -05:00
Gabe Black
156cf0db51 Change rename to rename the flattened register index instead of the architectural one. 
--HG--
extra : convert_revision : 757866ad7a3c8be7382e1ffa71c60bc00c861f6f
 2006-12-06 05:55:23 -05:00
Gabe Black
6456cb535c Added in endianness conversion on memory accesses as the data goes out. This will break the checker! 
--HG--
extra : convert_revision : b8191cab09ab8f3ced05693293f058382319ed8e
 2006-12-06 05:54:16 -05:00
Gabe Black
20340b5e26 Change how optional delay slot instructions are detected and squashed. 
--HG--
extra : convert_revision : ffd019d4adc2fbbc0a663d8dc6ef73edce12511b
 2006-12-06 05:51:18 -05:00
Gabe Black
8a21635eff Get rid of some typedefs which were hardly used, and move some stuff back here that shouldn't be in the architecture specific DynInst classes. 
--HG--
extra : convert_revision : dad0d7191acf773c16dc3ed9dd911f5e8bfc08b3
 2006-12-06 05:48:59 -05:00
Gabe Black
dc105934f3 Change to use -return_value.value like other implementations. 
--HG--
extra : convert_revision : 513422c1c8c24f3662e6a423d13ee033424aa44b
 2006-12-06 05:47:19 -05:00
Gabe Black
bf5f6c6430 Some changes for misc regs which were changed into unofficial integer registers, and moved the flattenIndex function into the register file. 
--HG--
extra : convert_revision : 6b797c793a6c12c61a23f0f78a1ea1c88609553e
 2006-12-06 05:46:44 -05:00
Gabe Black
5ad1731a12 Reorganize the includes and add an include for misc.hh. 
--HG--
extra : convert_revision : 484b2d07a1e8b3879c35d80bf16b73fd0cc9be1f
 2006-12-06 05:45:18 -05:00
Gabe Black
643cb6dd81 Added some debug output, and made sure not to accidentally ask for the result of a store conditional. 
--HG--
extra : convert_revision : d36ff9e2343fdf78a3bc16a1348975fdba5c55e2
 2006-12-06 05:44:31 -05:00
Gabe Black
a36a59e8d7 Some basic fix ups, and CWP is no longer set explicitly. 
--HG--
extra : convert_revision : 1dde5594a2bcfd9fb5ad974360b3dc035f1624e5
 2006-12-06 05:43:25 -05:00
Gabe Black
c541be3a48 Changed the integer register file to work with flattened indices. 
--HG--
extra : convert_revision : c5153c3c712e5d18b5233e1fd205806adcb30654
 2006-12-06 05:42:09 -05:00
Gabe Black
4d8a0541dd Change MIPS's setSyscallReturn to use a thread context. 
--HG--
extra : convert_revision : 618f8404ec5380615e28170d761b2fcdf9c07d96
 2006-12-06 05:41:08 -05:00
Gabe Black
a3f351ab59 Added basic flatten function for mips. 
--HG--
extra : convert_revision : 2c32851584001734d139f36c4d58c5e61067fcfc
 2006-12-06 05:40:11 -05:00
Steve Reinhardt
1c28682cea Don't compress data on writebacks unless it's actually necessary. 
--HG--
extra : convert_revision : 7a068e28f9ea2f6aab57be7133b47bda72d10302
 2006-12-05 07:16:36 -08:00
Gabe Black
12c5bd2305 Move the SyscallReturn class into sim/syscallreturn.hh. Also move some miscregs into the integer register file so they get renamed. 
src/arch/alpha/syscallreturn.hh:
src/arch/mips/syscallreturn.hh:
src/sim/syscallreturn.hh:
    Move the SyscallReturn class into sim/syscallreturn.hh
src/arch/sparc/faults.cc:
src/arch/sparc/isa/operands.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/arch/sparc/process.cc:
src/arch/sparc/sparc_traits.hh:
    Move some miscregs into the integer register file so they get renamed.

--HG--
extra : convert_revision : df5b94fa1e7fdca34816084e0a423d6fdf86c79b
 2006-12-05 01:55:02 -05:00
Steve Reinhardt
5fbf3aa471 Turn cache MissQueue/BlockingBuffer into virtual object 
instead of template parameter.

--HG--
extra : convert_revision : fce0fbd041149b9c781eb23f480ba84fddbfd4a0
 2006-12-04 09:10:53 -08:00
Steve Reinhardt
7a1120ab20 Merge vm1.(none):/home/stever/bk/newmem-head 
into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 321f7fcc8bd6c6aaaab92d10172814f4d07d5e65
 2006-12-02 22:26:40 -08:00
Steve Reinhardt
e6d7e8af21 Support better param conversions to/from numeric subclasses. 
--HG--
extra : convert_revision : 2ccb75b0912a384789458710fd9bbb65626f839e
 2006-12-02 22:24:52 -08:00