gem5/src
Gabe Black f410d5f4e0 Don't have "predict" set the predicted target of the instruction. Do that explicitly when you use predict.
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extra : convert_revision : 8b613bb365b31ffaef1cea9fd789abe46219bdcf
2006-12-16 07:39:44 -05:00
..
arch Made changes to CWP be non speculative. 2006-12-16 07:10:58 -05:00
base Make cache compression policy a runtime virtual thing 2006-12-02 22:22:58 -08:00
cpu Don't have "predict" set the predicted target of the instruction. Do that explicitly when you use predict. 2006-12-16 07:39:44 -05:00
dev Create a stub t1000 platform. 2006-11-14 15:14:27 -05:00
doxygen Fix up doxygen. 2006-08-14 19:25:07 -04:00
kern Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha specific DepTag constants. 2006-11-09 21:30:48 -05:00
mem Merge zizzer:/bk/newmem/ 2006-12-12 18:10:00 -05:00
python Merge zizzer:/bk/newmem/ 2006-12-12 18:10:00 -05:00
sim Add in constants which let you explicitly check if endian conversion would do anything. This was needed for a case where a piece of data was within a larger data type. When the larger data type was swapped, the location of the smaller data type would move. 2006-12-16 07:37:33 -05:00
unittest Merge iceaxe.:/Volumes/work/research/m5/head 2006-06-11 22:01:34 -04:00
Doxyfile Fix up doxygen. 2006-08-14 19:25:07 -04:00
SConscript Turn cache MissQueue/BlockingBuffer into virtual object 2006-12-04 09:10:53 -08:00