gem5/src
Gabe Black ef942ceecb Moved the RegIdx arrays to the base dyninst.
--HG--
extra : convert_revision : d705cde25c2cf1add20669e99d086add49141518
2006-12-06 11:37:39 -05:00
..
arch Made the alpha setSyscallReturn take a ThreadContext pointer instead of a RegFile *. 2006-12-06 11:33:37 -05:00
base add warn_once which will print any given warning message 2006-11-16 13:18:21 -08:00
cpu Moved the RegIdx arrays to the base dyninst. 2006-12-06 11:37:39 -05:00
dev Create a stub t1000 platform. 2006-11-14 15:14:27 -05:00
doxygen Fix up doxygen. 2006-08-14 19:25:07 -04:00
kern Moved the Alpha MiscRegFile into it's own file, and got rid of the Alpha specific DepTag constants. 2006-11-09 21:30:48 -05:00
mem Merge zizzer:/bk/newmem 2006-12-06 06:05:28 -05:00
python Added a parameter to set memory to zero. This is to support Legion, and once we can make our own hypervisor binary, we probably won't need it. 2006-11-22 23:09:27 -05:00
sim Move the SyscallReturn class into sim/syscallreturn.hh. Also move some miscregs into the integer register file so they get renamed. 2006-12-05 01:55:02 -05:00
unittest Merge iceaxe.:/Volumes/work/research/m5/head 2006-06-11 22:01:34 -04:00
Doxyfile Fix up doxygen. 2006-08-14 19:25:07 -04:00
SConscript Add TRACING_ON setting for m5.prof. 2006-11-27 02:16:24 -05:00