dev/ide_ctrl.cc:
generalize these #defs
dev/ide_ctrl.hh:
put these in pcireg.h
dev/ns_gige.cc:
do i need io_enable? and assert will fail if i actually need to implement it, which may give clue as to wehtehr i need to implmeent the mem_enable and bm_enable stuff.
dev/ns_gige.hh:
implement this in case it's needed
dev/pcireg.h:
put these defs in pcireg instead
--HG--
extra : convert_revision : 5e3581b5da17410f943907139bd479f15d2231e8
dev/ns_gige.cc:
fix serialization and move regsReset into the cc file
dev/ns_gige.hh:
put regsReset into cc instead of here in hh
--HG--
extra : convert_revision : 3a8796fa583e0765503104a9dbe28cc69f1a8fa9
busbridges. Also small fix for gcc 3.3.3.
dev/etherpkt.hh:
Gcc 3.3.3 wants assert.h to be include in this file.
dev/ide_ctrl.cc:
after unserialization we need to tell the busbridges what addresses to
respond to.
--HG--
extra : convert_revision : a421197a5be07761bdef571d0a9406d77788e270
3) add some new functions to etherpkt. 4) checkin the nice ping_linux.ini that i've been using.
dev/etherpkt.hh:
remove the packet headers nate hated so much.
also add some new functionality regarding packets, like isIpHdr(), etc.
dev/ns_gige.cc:
improve the code given the nice new functions offered in etherpkt
--HG--
extra : convert_revision : 2e27f5a8dca5323c0fa22d3c51af44a35f6be1a2
and started cleaning up config files.
arch/alpha/isa_desc:
Made implementation of cttz and ctlz more compact
base/remote_gdb.cc:
Added comment about PALcode debugger accesses
dev/baddev.cc:
dev/baddev.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
Cleaned up includes and changed device from FunctionalMemory to
PioDevice for detailed boot
dev/ns_gige.cc:
The ethernet dev uses two BARs, and the first bars size was being set
incorrectly.
dev/tsunamireg.h:
I don't know why we were using the superpage as the PCI memory addr.
Changed and works correctly with detailed boot.
--HG--
extra : convert_revision : b535e76612cb90b544305dc1aa8c5e0e774564bd
the source tree for *.odesc files every time we run the script.
This is now factored out into load_odesc.py, which should be used
to generate m5odescs.py, which is then used as the source of object
& parameter definitions.
util/config/m5configbase.py:
- Move odesc loading code to separate load_odescs.py, so maybe someday
that can be done once at build time.
- Print out children of a node in the order they are added.
- Automatically assign a parent-less node to the first node for which it
is used as the value of a parameter. (Easier demonstrated than explained.)
- Calculate object paths dynamically when requested rather than trying
to keep them up to date as objects get assigned to parents.
--HG--
rename : util/config/m5config.py => util/config/m5configbase.py
extra : convert_revision : 2183a09d32f3862ab377e0a929715f30505a03cb
cpu/trace/reader/m5_reader.cc:
Add thread num.
cpu/trace/trace_cpu.cc:
Increase thread count to 4, might want to make this a parameter (but it only really costs us storage).
--HG--
extra : convert_revision : 97cd7843668a3ef85aad06e3180dc04d2ca30ac1
dev/tsunami_io.cc:
Timers don't need to be rescheduled cause they aren't scheduled by
the default constructor
--HG--
extra : convert_revision : afb68e4f0c4e2a2c98f0037e061752690080a503
dev/ide_ctrl.cc:
Properly serialize/unserialize the PciDev base class to get it to remap
the MMU
dev/ns_gige.cc:
dev/ns_gige.hh:
Remove the "addr" paramter from the constructor and change the device
to use PCI based MMU mappings only
dev/pciconfigall.cc:
Change comments
dev/pcidev.cc:
Properly setup the MMU after a serialize
--HG--
extra : convert_revision : 4b2e7ba58e3c24fac1ff6f80635e704d6ecc0eff
Linux 2.6 with DMA support
dev/ide_disk.cc:
Add debug infomation for DMA transfers and fix handling of PRD pointer
values
dev/ide_disk.hh:
Reduce buffer (MAX_DMA) size to 64K
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
Add handling of PCTL register and also fix the translate from PCI to DMA
addresses which was incorrect
--HG--
extra : convert_revision : 562f55fa1c7099ad0f5a23f59dec2c8ec7601d43
virtual function in alphaaccess.cc
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/platform.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_io.hh:
Removed dynamic cast to get interrupt frequency and replaced with a
virtual function
--HG--
extra : convert_revision : 01f514a33d8f76c6527ab25a713d5c86f9fd646e
PIO writes. This was mainly related to not shadowing the status register
properly, and also not setting some of the status bits expected by the
operating system for the PIO write protocol.
--HG--
extra : convert_revision : fcdfd588be6e4f237aa6057889f0b3bdf4ea7631
way a Tru64 system can be either Tlaser (by default) or Tsunami.
Added debugSymbolTable to Tru64 for symbol printing in InstExec Trace
cpu/exetrace.cc:
Fixed bug if debugSymbolTable doesn't exist, we shouldn't try to
look something up in it.
kern/tru64/tru64_system.hh:
Added ability to specify system type/revision in config file. This
way a Tru64 system can be either Tlaser (by default) or Tsunami.
--HG--
extra : convert_revision : c69a7411f0aa118ca5a766e43b7ceb7a5bb04cdf
dev/tsunami_cchip.hh:
clean up some comments
kern/linux/linux_syscalls.cc:
Cleaned up spacing of syscall numbers
kern/linux/linux_system.hh:
Added doxygen comments
--HG--
extra : convert_revision : 23ecdaa92a208458dd5c5d3c68ac9012ce2690da
Got rid of two inconsistent sets of strings that corresponded
to this enum, and replaced with a single set that clearly
matches the enum names.
arch/alpha/isa_desc:
arch/isa_parser.py:
cpu/full_cpu/op_class.hh:
Renamed OpClass enum members.
--HG--
extra : convert_revision : bf596f7568a20b2e77c07ac349f253135141aef4
base/stats/mysql.hh:
Rename of Statsistics namespace to stats... merge from head
--HG--
extra : convert_revision : a5a7f6268b35e75fba1b1800a74fcd6dbd09d974
dev/baddev.hh:
dev/pcidev.hh:
dev/tsunami.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
Added doxygen comments
dev/pciconfigall.hh:
Added doxygen comments. Made the hlist of devices private and provided
members to modify the data.
dev/pcidev.cc:
updated for change in pciconfigall
dev/tsunami_pchip.cc:
Deleted commented out code we don't need
kern/linux/linux_syscalls.cc:
Simplified the number -> name conversion.
kern/linux/linux_syscalls.hh:
Removed StandardNumber and replaced with Number.
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
LinuxSkipIdeDelay50msEvent was simply the same as the SkipFunc event,
so I removed it. Same with with LinuxSkipFuncEvent.
--HG--
extra : convert_revision : 1508c335f87d90373f5772f3a0407ea13e858d7e
arch/alpha/ev5.cc:
Updated to support new forms of setIntReg and setFloatRegDouble. Will need to be cleaned up in the future.
arch/isa_parser.py:
Added in FastCPU model.
--HG--
extra : convert_revision : 384a27efcb50729ea6c3cc11653f395c300e48db
arch/alpha/ev5.cc:
Added templatized processInterrupts() function that can be used by all of the CPU models.
arch/alpha/isa_desc:
Merged in changes to remove CPU dependence.
arch/isa_parser.py:
Merged in changes.
cpu/static_inst.hh:
Includes FastCPU execute methods.
--HG--
extra : convert_revision : fcaa1dca35a9b316c73982bec8680df564f50bd8
Also various changes to make the CPU model less ISA dependent, which includes moving the code that checks for interrupts up to the ISA level, moving code that zeroes the zero registers up to the ISA level, and removing opcode and ra from the regfile.
arch/alpha/alpha_memory.cc:
The regfile has been changed so it no longer has the opcode and ra. Instead the xc holds the actual instruction, and from there the opcode and ra can be obtained with OPCODE() and RA().
arch/alpha/ev5.cc:
Moved code that once existed within simpleCPU to ev5, and templatized it.
This way the CPU models can call processInterrupts and the ISA specific interrupt handling is left to the ISA's code.
Also moved ISA specific zero registers from simpleCPU to here.
arch/alpha/ev5.hh:
Added macros for obtaining the opcode and ra from the instruction itself, as there is no longer opcode or ra in the regfile.
arch/alpha/isa_desc:
Added in declarations for the FastCPU model.
arch/alpha/isa_traits.hh:
Removed opcode and ra from the regfile. The xc now holds the actual instruction, and the opcode and ra can be obtained through it.
Also added the declaration for the templated zeroRegisters() function, which will set the zero registers to 0.
arch/isa_parser.py:
Added in FastCPUExecContext so it will generate code for the FastCPU model as well.
cpu/exec_context.cc:
Added in a more generic trap function so "ev5_trap" doesn't need to be called. It currently still calls the old method, with plans for making this ISA dependent in the future.
cpu/exec_context.hh:
Exec context now has the instruction within it. Also added methods for exec context to read an instruction from memory, return the current instruction, and set the instruction if needed.
Also has declaration for more generic trap() function.
cpu/simple_cpu/simple_cpu.cc:
Removed references to opcode and ra, and instead sets the xc's instruction with the fetched instruction.
cpu/static_inst.hh:
Added declaration for execute() using FastCPUExecContext.
--HG--
extra : convert_revision : 0441ea3700ac50b733e485395d4dd4ac83666f92
