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Author SHA1 Message Date
Lisa Hsu
ee777f35c2 interrupts.hh: 
make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build

src/arch/sparc/interrupts.hh:
    make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build

--HG--
extra : convert_revision : 5f469d0cf897479b42703104cd801a8ef923fcae
 2006-11-14 12:59:57 -05:00
Ron Dreslinski
21dc65bc47 If all the targets aren't satisfied, reinitialize the packet. 
--HG--
extra : convert_revision : 5b0a977a162a1b881b97a3185fb386cc76632a4a
 2006-11-14 10:09:13 -05:00
Ron Dreslinski
8155e61a60 Update atomic and functional paths for snoops as well 
--HG--
extra : convert_revision : 566d73438efb87ca683e4dee23454d880db3dfc7
 2006-11-14 01:38:42 -05:00
Gabe Black
7632198a6e Merge 141.212.106.238:/home/gblack/m5/newmemmemops 
into  zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem

--HG--
extra : convert_revision : cda58e6e63f2f909b85a510fb76d35d49d8042b9
 2006-11-14 01:31:37 -05:00
Gabe Black
20730b790c Set hpstate to be what I'm assuming Legion is. 
--HG--
extra : convert_revision : 0be66513cb0cff07c0c2b50c97c1ea74d52b0dc9
 2006-11-14 01:30:34 -05:00
Gabe Black
c2ceaa887e Make sure a POR doesn't clobber the value of the hpstate. 
--HG--
extra : convert_revision : 4504f08fd94792819bd4419bbd2e0ebd1d7f29e9
 2006-11-14 01:29:11 -05:00
Gabe Black
6b95f24145 Fix up the disassembly a little. 
--HG--
extra : convert_revision : 7bdf68f445b79b1b5dbcdfa5fa1005c68d03724c
 2006-11-14 01:28:11 -05:00
Gabe Black
8d234a4bc5 Merge 141.212.106.238:/home/gblack/m5/newmemmemops 
into  zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem

--HG--
extra : convert_revision : 753831a9f6f79d07e6ee122ab894e24161d2e722
 2006-11-14 01:23:59 -05:00
Ron Dreslinski
ac309071af Update phase param in the .py file for the cpus 
--HG--
extra : convert_revision : cd2eb8c00adcb34b8693a4d1a66187927c0f6803
 2006-11-14 01:13:26 -05:00
Ron Dreslinski
4135dd48ed Update bus bridges now that snoop ranges are passed properly 
src/mem/bridge.cc:
    Update brdiges, now that snoop addresses are properly forwarded.
    Bus bridge should only handle snoops on the second phase (SNOOP_COMMIT)
src/mem/bus.cc:
src/mem/bus.hh:
    Make sure if a busBridge has access to both things that snoop and things that respond it only takes the request once

--HG--
extra : convert_revision : 26cc9ee4429be45d4476fa435e0e9a54843c2509
 2006-11-14 01:12:52 -05:00
Ron Dreslinski
7babf6b3a8 Make cpu's capable of having a phase shift 
--HG--
extra : convert_revision : 7f082ba5c1cd2445aec731950c31a877aac23a75
 2006-11-14 01:10:36 -05:00
Ron Dreslinski
903a618714 Fix a bug to handle the fact that a CPU can send Functional accesses while a sendTiming has not returned in the call stack. 
src/mem/cache/base_cache.cc:
    Sometimes a functional access comes while waiting on a outstanding packet being sent.
    This could be because Timing CPU does some post processing on the recvTiming which send functional access.
    Either the CPU should leave the pkt/req around (so They can be referenced in the mem system). Or the mem
    system should remove them from outstanding lists and reinsert them if they fail in the sendTiming.

    I did the later, eventually we should consider doing the former if that is the correct behavior.

--HG--
extra : convert_revision : be41e0d2632369dca9d7c15e96e5576d7583fe6a
 2006-11-13 22:37:22 -05:00
Ron Dreslinski
db0895084d Merge zizzer:/bk/newmem 
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 253766a17bb5e109f8ad76b3c54e443db5274ef5
 2006-11-13 21:59:50 -05:00
Ron Dreslinski
69e183941f If we didn't satisfy all targets, reset the packet we are requesting with. 
--HG--
extra : convert_revision : 736372131b046eccf3520292fb3c086dc568d918
 2006-11-13 21:34:25 -05:00
Ron Dreslinski
9b6fd56dd5 Fix some errors related to snooping and functional access in the bus 
src/mem/bus.cc:
    Only call snoop once per port, need to fix it so snoop ranges that overlap aren't added to list
    Functional accesses that call snoop and it goes to a higher bus may change the src, reset it after each snoop.

--HG--
extra : convert_revision : 7276059c798a85cb9d138ccc5531298ecd055c13
 2006-11-13 21:33:01 -05:00
Ron Dreslinski
6c5c51338d Fix problems with snoop ranges not working properly on functional accesses 
src/mem/bus.cc:
    Actually return the snoop list when asked for it.
    Don't get stuck in infinite functional loops

--HG--
extra : convert_revision : 8e6dafbd10b30d48d28b6b5d4b464e8e8f6a3ddc
 2006-11-13 19:56:34 -05:00
Ron Dreslinski
dfc82bdcfc Changes needed for a bus from CPU->L1 
src/cpu/simple/atomic.cc:
    Make the atomic cpu return 0 on snoops.

--HG--
extra : convert_revision : aad96ad36e0c764c7cfef8b0c8e97877574f5845
 2006-11-13 19:12:45 -05:00
Ron Dreslinski
356a4f9f59 Since cpus now send out snoop ranges, remove it from the cache. 
--HG--
extra : convert_revision : 82882eb131aa66eba9f281b64db21d5cbfefb1b9
 2006-11-13 19:00:50 -05:00
Ron Dreslinski
a962fc4f56 Make CPU models signal to update the snoop ranges 
--HG--
extra : convert_revision : 717b62510f28a69af99453309fbbb458359eeb2a
 2006-11-13 18:51:16 -05:00
Lisa Hsu
69623a892e main.i: 
swig still thought the default arg for simulate() was -1, make it MaxTick

--HG--
extra : convert_revision : 2bcbef7e5e5d28cf55645fdc53d43e3953b1a11c
 2006-11-13 16:18:47 -05:00
Ron Dreslinski
023fccff0e Update splash2 config files 
configs/splash2/run.py:
    Fix MaxTick for splash configs
configs/splash2/cluster.py:
    Add a config that allows clusters of CPU's to be attached to a single L1

--HG--
extra : convert_revision : 1bb0a0c5f4889316940a9858be90ae2eaa849f1a
 2006-11-13 16:09:47 -05:00
Nathan Binkert
afed455e77 Expose debugBreakCycle through swig and get rid of 
the Debug param context

--HG--
extra : convert_revision : 40e9dcfa9faedbe0c90a43f908f20a7c14ded6a4
 2006-11-13 12:20:08 -08:00
Nathan Binkert
2370e638ce Clean up comment 
--HG--
extra : convert_revision : 75c6415c49305e2f8cf7f833c66a46a4dee503ea
 2006-11-13 12:18:36 -08:00
Ali Saidi
ef5b842247 Parse CC/CXX early so that we use the correct compiler for testing dependencies/versions/libraries/etc 
--HG--
extra : convert_revision : b34ee03e44b35df30b746c4c570316db75d6ffe5
 2006-11-13 13:26:36 -05:00
Kevin Lim
fd213f7270 Merge ktlim@zizzer:/bk/newmem 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : 6ef2249bfa3f7149830efdb42a313422090da7d7
 2006-11-13 02:49:13 -05:00
Kevin Lim
41a9196f60 More interrupt reworking. 
--HG--
extra : convert_revision : 40dfbb72c4e418c54e909c54dad5fe6ef7017cb4
 2006-11-13 02:49:03 -05:00
Steve Reinhardt
51d8c59ef8 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : faab7569deefde94c20133b2f70a8567bcaa2960
 2006-11-12 22:04:00 -08:00
Steve Reinhardt
0f633c5fee Make setRegWithEffect do something in SE mode. 
--HG--
extra : convert_revision : 88fdaa403fe6d083f8c8fc064cb0d0d6a8b8daf8
 2006-11-12 22:03:42 -08:00
Kevin Lim
4c21fab575 Change warn to DPRINTF. 
--HG--
extra : convert_revision : 746bdf92334d220158eb0eb6bf113b4dcedbb354
 2006-11-13 00:26:38 -05:00
Kevin Lim
b0db4e4dcf Update output refs. Some FS statistics will change (namely the ITB) due to the recent TLB changes. Now PAL mode accesses are counted as hits in the TLB. 
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr:
tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt:
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini:
tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini:
tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out:
    Update refs.

--HG--
extra : convert_revision : 6798c5753d4d7bd7b5667d59cf564012b781ce8a
 2006-11-13 00:24:22 -05:00
Kevin Lim
9e53eed88a Fix typo. 
--HG--
extra : convert_revision : 05db10e20d33302fe830d5759b8881b1233aca87
 2006-11-12 23:31:29 -05:00
Kevin Lim
8a0cbbe27b Fix for regression failure. 
src/cpu/o3/fetch_impl.hh:
    Fetch needs to make sure it isn't waiting on an Icache access.

--HG--
extra : convert_revision : b53eb58b9e5a00bdb394134586d1f84f84d1c6e1
 2006-11-12 23:30:09 -05:00
Gabe Black
14cb2264c8 Merge zizzer.eecs.umich.edu:/bk/newmem/ 
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : eed3b6a650635d43fe75c2158c8417647af640d9
 2006-11-12 22:36:22 -05:00
Kevin Lim
3052632b68 Merge ktlim@zamp:./local/clean/tmp/test-regress 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

--HG--
extra : convert_revision : b98236507bb8996ce605b48b5a5a6a7aac297dc5
 2006-11-12 21:57:58 -05:00
Kevin Lim
437436a2f7 Fix for non-FS compile. 
--HG--
extra : convert_revision : 661b412b0ae670181b89cb7dbc5e9d813804aa7a
 2006-11-12 21:49:51 -05:00
Nathan Binkert
d2d4431752 Create a module called internal where swigged stuff goes. 
Rename cc_main to internal.main

--HG--
extra : convert_revision : e938005f600fbf8a43435e29426a948f4501f072
 2006-11-12 18:49:16 -08:00
Kevin Lim
12e26c68c3 Updates to support new interrupt processing and removal of PcPAL. 
src/arch/alpha/interrupts.hh:
    No need for this now that the ThreadContext is being used to set these IPRs in interrupts.
    Also split up the interrupt checking from the updating of the IPL and interrupt summary.
src/arch/alpha/tlb.cc:
    Check the PC for whether or not it's in PAL mode, not the addr.
src/cpu/o3/alpha/cpu.hh:
    Split up getting the interrupt from actually processing the interrupt.
src/cpu/o3/alpha/cpu_impl.hh:
    Splut up the processing of interrupts.
src/cpu/o3/commit_impl.hh:
    Update for ISA-oriented interrupt changes.
src/cpu/o3/fetch_impl.hh:
    Fix broken if statement from PcPAL updates, and properly populate the request fields.

    Also more debugging output.
src/cpu/ozone/cpu_impl.hh:
    Updates for ISA-oriented interrupt stuff.
src/cpu/ozone/front_end_impl.hh:
    Populate request fields properly.
src/cpu/simple/base.cc:
    Update for interrupt stuff.

--HG--
extra : convert_revision : 9bac3f9ffed4948ee788699b2fa8419bc1ca647c
 2006-11-12 20:15:30 -05:00
Ron Dreslinski
6098f57b08 Update for maxtick in splash2/memtest configs 
configs/example/memtest.py:
configs/splash2/run.py:
    Update for maxtick

--HG--
extra : convert_revision : 94106625be1ebc2b614db16720a4861e47222c0b
 2006-11-12 11:42:07 -05:00
Ron Dreslinski
fa41791a57 Update refs for functional access fixes 
--HG--
extra : convert_revision : aa34e0e7254daf20ecb7c14d430f08927a8fb9ca
 2006-11-12 11:07:34 -05:00
Ron Dreslinski
1d5d9c83b4 Merge zizzer:/bk/newmem 
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 498304c24435437f8f1942bb8aeafe69ba22a089
 2006-11-12 10:41:18 -05:00
Ron Dreslinski
5edfaefc78 Physical memory overrides the tport version of recvFunctional, need to do the 
check here for responses that match as well

--HG--
extra : convert_revision : 69c3628a381a9da885fab0272abf40c3411a5f0f
 2006-11-12 09:30:12 -05:00
Ron Dreslinski
a200bccc20 Handle packets being deleted by lower level properly. 
Fixes for Mem Leak associated with Writebacks.

src/mem/cache/miss/mshr_queue.cc:
    Fixes for Mem Leak associated with Writebacks. (Double Delete removed)

--HG--
extra : convert_revision : 7a52ddd57da35995896f2c4438a58aa53f762416
 2006-11-12 09:06:15 -05:00
Ron Dreslinski
29cefcbf13 Don't insert reponses into the list more than once 
If you get inserted in the front, reschedule the event

--HG--
extra : convert_revision : eccbacf5ec85600e5b68eb554fee2c0e2b65e965
 2006-11-12 07:16:34 -05:00
Ron Dreslinski
11accacf7c Move code before a early return to make sure it is executed on all paths 
--HG--
extra : convert_revision : cfdd5b6911422fbb733677c43d027aa4407fbc85
 2006-11-12 06:44:05 -05:00
Ron Dreslinski
b22d390721 Yet another small bug in mem system related to flow control 
src/mem/cache/cache_impl.hh:
    When upgrades change to readEx make sure to allocate the block
    Fix dprintf

--HG--
extra : convert_revision : 8700a7e47ad042c8708302620b907849c4bfdded
 2006-11-12 06:36:33 -05:00
Ron Dreslinski
c577665040 Fix functional access errors related to delayed respnoses in cachePort 
src/mem/cache/base_cache.cc:
    On a delayed response, be sure to call the fixPacket wrapper to toggle hasData flag.
src/mem/packet.cc:
src/mem/packet.hh:
    Create a wrapper to toggle the hasData flag on delayed responses

--HG--
extra : convert_revision : 1ced8d4e3dc12a059fb7636d59e429cd3dd46901
 2006-11-12 06:35:39 -05:00
Nathan Binkert
8354cfc715 Fix Typo 
--HG--
extra : convert_revision : 4f5b610f364876b29ad0e04f1757e4b42d1f2bd8
 2006-11-11 23:57:20 -08:00
Nathan Binkert
3f280bb2e8 set TRACING_ON one way or another explicitly in the 
SConscript file instead of basing it on DEBUG

--HG--
extra : convert_revision : 6e6807cc4350ef92baeaaabfeb3dc0bb785128ba
 2006-11-11 20:46:56 -08:00
Nathan Binkert
aec0afd59f Delete the actual PseudoInst file 
--HG--
extra : convert_revision : 54e3dfbc1022fcc663a9c0e67f6434395d1fe33c
 2006-11-11 17:30:37 -08:00
Nathan Binkert
b16e559177 Get rid of the ParamContext for pseudo instructions and move 
the parameters to the BaseCPU object.

--HG--
extra : convert_revision : 557292cffb40918133647b0c9ac653ee5112df2e
 2006-11-11 17:22:10 -08:00