Commit graph

9180 commits

Author SHA1 Message Date
Andreas Hansson
d53d04473e Clock: Rework clocks to avoid tick-to-cycle transformations
This patch introduces the notion of a clock update function that aims
to avoid costly divisions when turning the current tick into a
cycle. Each clocked object advances a private (hidden) cycle member
and a tick member and uses these to implement functions for getting
the tick of the next cycle, or the tick of a cycle some time in the
future.

In the different modules using the clocks, changes are made to avoid
counting in ticks only to later translate to cycles. There are a few
oddities in how the O3 and inorder CPU count idle cycles, as seen by a
few locations where a cycle is subtracted in the calculation. This is
done such that the regression does not change any stats, but should be
revisited in a future patch.

Another, much needed, change that is not done as part of this patch is
to introduce a new typedef uint64_t Cycle to be able to at least hint
at the unit of the variables counting Ticks vs Cycles. This will be
done as a follow-up patch.

As an additional follow up, the thread context still uses ticks for
the book keeping of last activate and last suspend and this should
probably also be changed into cycles as well.
2012-08-28 14:30:31 -04:00
Andreas Hansson
d14e5857c7 Port: Stricter port bind/unbind semantics
This patch tightens up the semantics around port binding and checks
that the ports that are being bound are currently not connected, and
similarly connected before unbind is called.

The patch consequently also changes the order of the unbind and bind
for the switching of CPUs to ensure that the rules are adhered
to. Previously the ports would be "over-written" without any check.

There are no changes in behaviour due to this patch, and the only
place where the unbind functionality is used is in the CPU.
2012-08-28 14:30:27 -04:00
Andreas Hansson
fb5dd28420 Checker: Bump the realview-o3-checker regression
This patch bumps the stats for the realview-o3-checker after fixing
the checker CPU in the previous patch.
2012-08-28 14:30:25 -04:00
Andreas Hansson
105ad88d35 Checker: Fix checker CPU ports
This patch updates how the checker CPU handles the ports such that the
regressions will once again run without causing a panic.

A minor amount of tidying up was also done as part of this patch.
2012-08-28 14:30:24 -04:00
Andreas Hansson
d090f4d930 swig: Disable unused value warning with llvm 3.1 compilers
This patch disables a warning for unused values which causes problems
when compiling the swig-generated sources using recent llvm-based
compilers like llvm-gcc and clang.
2012-08-28 14:30:22 -04:00
Anthony Gutierrez
5b1614de02 sim: fix overflow check in simulate because Tick is now unsigned 2012-08-27 20:53:20 -04:00
Nilay Vaish
85c7352462 Ruby: remove README.debugging and Decommissioning_note
These files were relevant when Ruby was part of GEMS. They are not required
any longer.
2012-08-27 14:57:46 -05:00
Nilay Vaish
0737837109 System: Remove redundant call to startupCPU 2012-08-27 01:14:46 -05:00
Nilay Vaish
9190940511 Ruby: Remove RubyEventQueue
This patch removes RubyEventQueue. Consumer objects now rely on RubySystem
or themselves for scheduling events.
2012-08-27 01:00:55 -05:00
Nilay Vaish
7122b83d8f Ruby Memory Vector: Allow more than 4GB of memory
The memory size variable was a 32-bit int. This meant that the size of the
memory was limited to 4GB. This patch changes the type of the variable to
64-bit to support larger memory sizes. Thanks to Raghuraman Balasubramanian
for bringing this to notice.
2012-08-27 01:00:54 -05:00
Nilay Vaish
1032bc72ed Regression: updates ruby.stats due to change in virtual network 2012-08-25 15:49:07 -05:00
Nilay Vaish
b422994fea MESI Protocol: Correct the virtual network in profile functions
The virtual network in a couple of places was incorrectly mentioned
as 3 in place of 1. This is being corrected.
2012-08-25 15:49:06 -05:00
Nilay Vaish
01f1430833 MESI Coherence Protocol: Add copyright notice 2012-08-25 13:16:45 -05:00
Andreas Hansson
2c1052cd4d DMA: Refactor the DMA device and align timing and atomic
This patch does a bunch of house-keeping updates on the DMA, including
indentation, and formatting, but most importantly breaks out the
response handling such that it can be shared between the atomic and
timing modes. It also removes a potential bug caused by the atomic
handling of responses only deleting the allocated request (pkt->req)
once the DMA action completes instead of doing so for every packet.

Before this patch, the handling of responses was near identical for
atomic and timing, but the code was simply duplicated. With this
patch, the handleResp method deals with the responses in both cases.

There are further updates to make after removing the NACKs, but that
will be part of a separate follow-up patch. This patch does not change
the behaviour of any regression.
2012-08-22 11:40:01 -04:00
Andreas Hansson
c60db56741 Packet: Remove NACKs from packet and its use in endpoints
This patch removes the NACK frrom the packet as there is no longer any
module in the system that issues them (the bridge was the only one and
the previous patch removes that).

The handling of NACKs was mostly avoided throughout the code base, by
using e.g. panic or assert false, but in a few locations the NACKs
were actually dealt with (although NACKs never occured in any of the
regressions). Most notably, the DMA port will now never receive a NACK
and the backoff time is thus never changed. As a consequence, the
entire backoff mechanism (similar to a PCI bus) is now removed and the
DMA port entirely relies on the bus performing the arbitration and
issuing a retry when appropriate. This is more in line with e.g. PCIe.

Surprisingly, this patch has no impact on any of the regressions. As
mentioned in the patch that removes the NACK from the bridge, a
follow-up patch should change the request and response buffer size for
at least one regression to also verify that the system behaves as
expected when the bridge fills up.
2012-08-22 11:39:59 -04:00
Andreas Hansson
a6074016e2 Bridge: Remove NACKs in the bridge and unify with packet queue
This patch removes the NACKing in the bridge, as the split
request/response busses now ensure that protocol deadlocks do not
occur, i.e. the message-dependency chain is broken by always allowing
responses to make progress without being stalled by requests. The
NACKs had limited support in the system with most components ignoring
their use (with a suitable call to panic), and as the NACKs are no
longer needed to avoid protocol deadlocks, the cleanest way is to
simply remove them.

The bridge is the starting point as this is the only place where the
NACKs are created. A follow-up patch will remove the code that deals
with NACKs in the endpoints, e.g. the X86 table walker and DMA
port. Ultimately the type of packet can be complete removed (until
someone sees a need for modelling more complex protocols, which can
now be done in parts of the system since the port and interface is
split).

As a consequence of the NACK removal, the bridge now has to send a
retry to a master if the request or response queue was full on the
first attempt. This change also makes the bridge ports very similar to
QueuedPorts, and a later patch will change the bridge to use these. A
first step in this direction is taken by aligning the name of the
member functions, as done by this patch.

A bit of tidying up has also been done as part of the simplifications.

Surprisingly, this patch has no impact on any of the
regressions. Hence, there was never any NACKs issued. In a follow-up
patch I would suggest changing the size of the bridge buffers set in
FSConfig.py to also test the situation where the bridge fills up.
2012-08-22 11:39:58 -04:00
Andreas Hansson
e317d8b9ff Port: Extend the QueuedPort interface and use where appropriate
This patch extends the queued port interfaces with methods for
scheduling the transmission of a timing request/response. The methods
are named similar to the corresponding sendTiming(Snoop)Req/Resp,
replacing the "send" with "sched". As the queues are currently
unbounded, the methods always succeed and hence do not return a value.

This functionality was previously provided in the subclasses by
calling PacketQueue::schedSendTiming with the appropriate
parameters. With this change, there is no need to introduce these
extra methods in the subclasses, and the use of the queued interface
is more uniform and explicit.
2012-08-22 11:39:56 -04:00
Andreas Hansson
70e99e0b91 Device: Remove overloaded pio_latency parameter
This patch removes the overloading of the parameter, which seems both
redundant, and possibly incorrect.

The PciConfigAll now also uses a Param.Latency rather than a
Param.Tick. For backwards compatibility it still sets the pio_latency
to 1 tick. All the comments have also been updated to not state that
it is in simticks when it is not necessarily the case.
2012-08-21 05:50:03 -04:00
Andreas Hansson
a81c969529 CPU: Remove overloaded function_trace_start parameter
This patch removes the overloading of the parameter, which seems both
redundant, and possibly incorrect.

The inorder CPU is particularly interesting as it uses a different
name for the parameter, and never make any use of it internally.
2012-08-21 05:49:43 -04:00
Andreas Hansson
5803309574 PacketQueue: Allow queuing in the same tick as desired send tick
This patch allows packets to be enqueued in the same tick as they are
intended to be sent. This does not imply they actually are sent that
tick, although that is possible.

This change is useful for module that use the queued ports primarly to
avoid handling the flow control involved in sending and retrying
packets.
2012-08-21 05:49:24 -04:00
Andreas Hansson
4be1ae3cf8 EventManager: Remove test for NULL pointer in constructor
This patch tidies up the EventManager constructor and prunes a corner
case where the EventManager would initialise its eventq pointer to
NULL. This would cause segmentation faults on actual use and should
never happen.
2012-08-21 05:49:18 -04:00
Andreas Hansson
016593f2e9 Clock: Make Tick unsigned and remove UTick
This patch makes the Tick unsigned and removes the UTick typedef. The
ticks should never be negative, and there was only one major issue
with removing it, caused by the o3 CPU using a -1 as an initial value.

The patch has no impact on any regressions.
2012-08-21 05:49:09 -04:00
Andreas Hansson
452217817f Clock: Move the clock and related functions to ClockedObject
This patch moves the clock of the CPU, bus, and numerous devices to
the new class ClockedObject, that sits in between the SimObject and
MemObject in the class hierarchy. Although there are currently a fair
amount of MemObjects that do not make use of the clock, they
potentially should do so, e.g. the caches should at some point have
the same clock as the CPU, potentially with a 1:n ratio. This patch
does not introduce any new clock objects or object hierarchies
(clusters, clock domains etc), but is still a step in the direction of
having a more structured approach clock domains.

The most contentious part of this patch is the serialisation of clocks
that some of the modules (but not all) did previously. This
serialisation should not be needed as the clock is set through the
parameters even when restoring from the checkpoint. In other words,
the state is "stored" in the Python code that creates the modules.

The nextCycle methods are also simplified and the clock phase
parameter of the CPU is removed (this could be part of a clock object
once they are introduced).
2012-08-21 05:49:01 -04:00
Andreas Hansson
4ebefc145a Checkpoint: Fix broken checkpointing functionality
This patch fixes the checkpointing by ensuring that the directory is
passer to the scriptCheckpoints function, and that the num_checkpoints
is not used before it is initialised.
2012-08-21 05:48:52 -04:00
Nilay Vaish
0160d51483 Ruby Banked Array: add copyrights 2012-08-19 13:05:53 -05:00
Jason Power
44b4c96253 Ruby: Add RubySystem parameter to MemoryControl
This guarantees that RubySystem object is created before the MemoryController
object is created.
2012-08-16 23:39:36 -05:00
Nilay Vaish
649e377937 Alpha System: override startup(), instead of loadState()
Alpha System was overriding loadState() function to setup some functional
event. The system tried to read/write to memory before the Ruby memory had
unserialized the state. With this patch, Alpha System overrides the
startup() function, and sets up functional events in this function. This
works because startup() is called after Ruby memory system has unserialized
the memory state.
2012-08-16 23:45:21 -05:00
Anthony Gutierrez
0b3897fc90 O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs
This patch fixes some problems with the drain/switchout functionality
for the O3 cpu and for the ARM ISA and adds some useful debug print
statements.

This is an incremental fix as there are still a few bugs/mem leaks with the
switchout code. Particularly when switching from an O3CPU to a
TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA
I haven't encountered any more assertion failures; now the kernel will
typically panic inside of simulation.
2012-08-15 10:38:08 -04:00
Anthony Gutierrez
5a648f2074 configs: add option for repeatedly switching back-and-forth between cpu types.
This patch adds a --repeat-switch option that will enable repeat core
switching at a user defined period (set with --switch-freq option).
currently, a switch can only occur between like CPU types. inorder CPU
switching is not supported.

*note*
this patch simply allows a config that will perform repeat switching, it
does not fix drain/switchout functionality. if you run with repeat switching
you will hit assertion failures and/or your workload with hang or die.
2012-08-15 10:38:07 -04:00
Ali Saidi
73e9e923d0 stats: Update stats for syscall emulation Linux kernel changes. 2012-08-15 10:38:05 -04:00
Ali Saidi
dd1b346584 sysemul: bump all linux versions of for syscal emulation to 3.0.
New tool chains seem to be looking for kernel versions newer than what
this this was previously set to. Also take this opportunity to change
the hostname we report in uname to sim.gem5.org.
2012-08-15 10:38:04 -04:00
Jason Power
11411cc9c7 Ruby: Clean up topology changes
This patch moves instantiateTopology into Ruby.py and removes the
mem/ruby/network/topologies directory. It also adds some extra inheritance to
the topologies to clean up some issues in the existing topologies.
2012-08-10 13:50:42 -05:00
Nilay Vaish
706e84f2b8 System: set kernel to null, if unspecified. 2012-08-08 13:40:32 -05:00
Marc Orr
7cef6b9bef syscall emulation: Enabled getrlimit and getrusage for x86.
Added/moved rlimit constants to base linux header file.

This patch is a revised version of Vince Weaver's earlier patch.
2012-08-06 19:52:56 -07:00
Steve Reinhardt
f4b424cd53 SETranslatingPortProxy: fix bug in tryReadString()
Off-by-one loop termination meant that we were stuffing
the terminating '\0' into the std::string value, which
makes for difficult-to-debug string comparison failures.
2012-08-06 16:57:11 -07:00
Steve Reinhardt
73ef8bd168 process: add progName() virtual function
This replaces a (potentially uninitialized) string
field with a virtual function so that we can have
a safe interface without requiring changes to the
eio code.
2012-08-06 16:55:34 -07:00
Steve Reinhardt
e232152db6 syscall_emul: clean up open() code a bit. 2012-08-06 16:55:28 -07:00
Steve Reinhardt
b647b48bf4 str: add an overloaded startswith() utility method
for various string types and use it in a few places.
2012-08-06 16:52:49 -07:00
Marc Orr
d55115936e syscall emulation: Clean up ioctl handling, and implement for x86.
Enable different whitelists for different OS/arch combinations,
since some use the generic Linux definitions only, and others
use definitions inherited from earlier Unix flavors on those
architectures.

Also update x86 function pointers so ioctl is no longer
unimplemented on that platform.

This patch is a revised version of Vince Weaver's earlier patch.
2012-08-06 16:52:40 -07:00
Nilay Vaish
62425b7a07 Simulation.py: move code related to checkpointing to functions
This patch moves the code related to checkpointing from the run() function to
several different functions. The aim is to make the code more manageable. No
functionality changes are expected, but since the code is kind of unruly, it
is possible that some change might have creeped in.
2012-08-06 18:14:32 -05:00
Nilay Vaish
d81a51a4c8 Config: change how cpu class is set
This changes the way in which the cpu class while restoring from a checkpoint
is set. Earlier it was assumed if cpu type with which to restore is not same
as the cpu type with the which to run the simulation, then the checkpoint
should be restored with the atomic cpu. This assumption is being dropped. The
checkpoint can now be restored with any cpu type, the default being atomic cpu.
2012-08-06 18:14:31 -05:00
Jason Power
6721b3e325 Ruby NetDest: add assert for bad element in netdest 2012-08-01 17:07:34 -05:00
Ali Saidi
6a70ef30a3 stats: revert pc-simple-timing-ruby-MESI_CMP_directory to before last update 2012-07-30 12:11:25 -04:00
Ali Saidi
19cc023cf5 stats: fix some miss-committed changes from the icache change 2012-07-28 13:48:04 -04:00
Nathanael Premillieu
fe2faa1975 util: Fix issues with style checker. 2012-07-27 16:08:05 -04:00
Ali Saidi
b1a58933e0 stats: update stats for icache change not allowing dirty data 2012-07-27 16:08:05 -04:00
Anthony Gutierrez
630068be6f dma: remove unused variable
this patch removes the actionInProgress field from the DmaPort class.
this variable is only defined and initiated in the ctor. it is never used.
2012-07-27 16:08:05 -04:00
Anthony Gutierrez
8133f2460f checker: make checker cpu id match its host's cpu id
when using the checker i ran into problems where an instruction reading the
cpu id register failed because the ids did not match, and hence, the result
of the instruction did not match. this patch ensures that the ids match so
this instruction does not fail. this problem only seemed to manifest itself
when multiple cores were in the system, either multi-core, or extra switched-
out cores present in the system.
2012-07-27 16:08:04 -04:00
Anthony Gutierrez
7bf14aedbf cache: don't allow dirty data in the i-cache
removes the optimization that forwards an exclusive copy to a requester on a
read, only for the i-cache. this optimization isn't necessary because we
typically won't be writing to the i-cache.
2012-07-27 16:08:04 -04:00
Anthony Gutierrez
2eb6b403c9 ARM: fix value of MISCREG_CTR returned by readMiscReg()
According to the A15 TRM the value of this register is as follows (assuming 16 word = 64 byte lines)
[31:29] Format - b100 specifies v7
[28] RAZ - b0
[27:24] CWG log2(max writeback size #words) - 0x4 16 words
[23:20] ERG log2(max reservation size #words) - 0x4 16 words
[19:16] DminLine log2(smallest dcache line #words) - 0x4 16 words
[15:14] L1Ip L1 index/tagging policy - b11 specifies PIPT
[13:4] RAZ - b0000000000
[3:0] IminLine log2(smallest icache line #words) - 0x4 16 words
2012-07-27 16:08:04 -04:00