Commit graph

2179 commits

Author SHA1 Message Date
Gabe Black
d43eb42d00 X86: Mark serializing macroops and regular instructions as such. 2010-08-23 09:44:19 -07:00
Gabe Black
69fc2af006 X86: Add a .serializing directive that makes a macroop serializing.
This directive really just tells the macroop to set IsSerializing and
IsSerializeAfter on its final microop.
2010-08-23 09:44:19 -07:00
Gabe Black
5a1dbe4d99 X86: Consolidate extra microop flags into one parameter.
This single parameter replaces the collection of bools that set up various
flavors of microops. A flag parameter also allows other flags to be set like
the serialize before/after flags, etc., without having to change the
constructor.
2010-08-23 09:44:19 -07:00
Min Kyu Jeong
e6a0be648e ARM: Improve printing of uop disassembly. 2010-08-23 11:18:42 -05:00
Min Kyu Jeong
d2fac84b95 ARM: Clean up flattening for SPSR adding 2010-08-23 11:18:41 -05:00
Gene Wu
a02d82f9f8 ARM: Implement DBG instruction that doesn't do much for now. 2010-08-23 11:18:41 -05:00
Gene Wu
d6736384b2 MEM: Make CLREX a first class request operation and clear locks in caches when it in received 2010-08-23 11:18:41 -05:00
Gene Wu
23626d99af ARM: Make sure that software prefetch instructions can't change the state of the TLB 2010-08-23 11:18:41 -05:00
Gene Wu
1fd104fc35 ARM: Don't write tracedata on writes, it might have been freed already. 2010-08-23 11:18:41 -05:00
Gene Wu
9db2ab8a62 ARM: Implement CLREX init/complete acc methods 2010-08-23 11:18:41 -05:00
Gene Wu
f29e09746a ARM: Fix Uncachable TLB requests and decoding of xn bit 2010-08-23 11:18:41 -05:00
Gene Wu
aa601750f8 ARM: For non-cachable accesses set the UNCACHABLE flag 2010-08-23 11:18:41 -05:00
Gene Wu
7405f4b774 ARM: Implement DSB, DMB, ISB 2010-08-23 11:18:41 -05:00
Gene Wu
aabf478920 ARM: Get SCTLR TE bit from reset SCTLR 2010-08-23 11:18:41 -05:00
Gene Wu
1f032ad345 ARM: Implement CLREX 2010-08-23 11:18:41 -05:00
Gene Wu
66bcbec96e ARM: BX instruction can be contitional if last instruction in a IT block
Branches are allowed to be the last instuction in an IT block. Before it was
assumed that they could not. So Branches in thumb2 were Uncond.
2010-08-23 11:18:41 -05:00
Min Kyu Jeong
92ae620be8 ARM: mark msr/mrs instructions as SerializeBefore/After
Since miscellaneous registers bypass wakeup logic, force serialization
to resolve data dependencies through them
* * *
ARM: adding non-speculative/serialize flags for instructions change CPSR
2010-08-23 11:18:41 -05:00
Min Kyu Jeong
5f91ec3f46 ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.
THis allows the CPU to handle predicated-false instructions accordingly.
This particular patch makes loads that are predicated-false to be sent
straight to the commit stage directly, not waiting for return of the data
that was never requested since it was predicated-false.
2010-08-23 11:18:40 -05:00
Min Kyu Jeong
7acf67971c ARM: adding genMachineCheckFault() stub for ARM that doesn't panic 2010-08-23 11:18:40 -05:00
Gene Wu
5486fa6612 ARM: DFSR status value for sync external data abort is expected to be 0x8 in ARMv7 2010-08-23 11:18:40 -05:00
Gene Wu
a993188034 ARM: Temporary local variables can't conflict with isa parser operands.
PC is an operand, so we can't have a temp called PC
2010-08-23 11:18:40 -05:00
Ali Saidi
0c434b7f56 ARM: Exclusive accesses must be double word aligned 2010-08-23 11:18:40 -05:00
Ali Saidi
5148c693d8 ARM: Add some registers for big loads/stores to support neon. 2010-08-23 11:18:40 -05:00
Ali Saidi
fc1730044e ARM: Decode neon memory instructions. 2010-08-23 11:18:40 -05:00
Gabe Black
d1362d582a ARM: Clean up the ISA desc portion of the ARM memory instructions. 2010-08-23 11:18:40 -05:00
Ali Saidi
230acc291c ARM: We don't currently support ThumbEE exceptions, so don't report that we do 2010-08-23 11:18:40 -05:00
Ali Saidi
bb5377899a ARM: Add system for ARM/Linux and bootstrapping 2010-08-23 11:18:40 -05:00
Ali Saidi
38cf6a164d ARM: Implement some more misc registers 2010-08-23 11:18:40 -05:00
Ali Saidi
b7b2eae6fa ARM: Fix an un-initialized variable bug 2010-08-23 11:18:39 -05:00
Ali Saidi
f2642e2055 Loader: Make the load address mask be a parameter of the system rather than a constant.
This allows one two different OS requirements for the same ISA to be handled.
Some OSes are compiled for a virtual address and need to be loaded into physical
memory that starts at address 0, while other bare metal tools generate
images that start at address 0.
2010-08-23 11:18:39 -05:00
Min Kyu Jeong
d4e83a4001 ARM: Finish the timing translation when taking a fault. 2010-08-23 11:18:39 -05:00
Dam Sunwoo
cb76111a7e ARM: Use a stl queue for the table walker state 2010-08-23 11:18:39 -05:00
Ali Saidi
ac575a9d82 Compiler: Fixes for GCC 4.5. 2010-08-23 11:18:39 -05:00
Gabe Black
fa01fbddeb X86: Get rid of unused file arguments.hh. 2010-08-22 18:42:23 -07:00
Gabe Black
4ad30a662d SPARC: Fix some style issues in utility.hh. 2010-08-22 18:39:39 -07:00
Gabe Black
5836023ab2 X86: Get rid of the unused getAllocator on the python base microop class.
This function is always overridden, and doesn't actually have the right
signature.
2010-08-22 18:24:09 -07:00
Steve Reinhardt
164a211f10 x86: minor checkpointing bug fixes 2010-08-17 05:20:39 -07:00
Steve Reinhardt
f064aa3060 sim: revamp unserialization procedure
Replace direct call to unserialize() on each SimObject with a pair of
calls for better control over initialization in both ckpt and non-ckpt
cases.

If restoring from a checkpoint, loadState(ckpt) is called on each
SimObject.  The default implementation simply calls unserialize() if
there is a corresponding checkpoint section, so we get backward
compatibility for existing objects.  However, objects can override
loadState() to get other behaviors, e.g., doing other programmed
initializations after unserialize(), or complaining if no checkpoint
section is found.  (Note that the default warning for a missing
checkpoint section is now gone.)

If not restoring from a checkpoint, we call the new initState() method
on each SimObject instead.  This provides a hook for state
initializations that are only required when *not* restoring from a
checkpoint.

Given this new framework, do some cleanup of LiveProcess subclasses
and X86System, which were (in some cases) emulating initState()
behavior in startup via a local flag or (in other cases) erroneously
doing initializations in startup() that clobbered state loaded earlier
by unserialize().
2010-08-17 05:17:06 -07:00
Gabe Black
52a90a5998 CPU: Tidy up endianness handling for mmapped "IPR"s. 2010-08-13 06:10:45 -07:00
Timothy M. Jones
97d245278d Power: The condition register should be set or cleared upon a system call
return to indicate success or failure.
2010-07-22 18:54:37 +01:00
Timothy M. Jones
8c76715979 Power: Provide a utility function to copy registers from one thread context
to another in the Power ISA.
2010-07-22 18:47:03 +01:00
Tushar Krishna
11bb678a80 Fix x86 XCHG macro-op to use locked micro-ops for all memory accesses 2010-07-21 09:55:57 -07:00
Gabe Black
8cec870568 ARM: Make an SRS instruction with a bad mode cause an undefined instruction fault. 2010-07-15 02:11:56 -07:00
Gabe Black
4e3183cb1e ARM: Adjust the FP_Base_DepTag to be larger than the largest int reg index. 2010-07-13 22:41:47 -07:00
Gabe Black
6697d41693 X86: Fix div2 flag calculation. 2010-06-25 00:21:48 -07:00
Nathan Binkert
86a93fe7b9 stats: only consider a formula initialized if there is a formula 2010-06-15 01:18:36 -07:00
Nathan Binkert
54d813adca stats: get rid of the never-really-used event stuff 2010-06-14 23:24:46 -07:00
Steve Reinhardt
d0af5e9df6 More minor gdb-related cleanup.
Found several more stale includes and forward decls.
2010-06-03 19:41:34 -07:00
Ali Saidi
d2186857b1 ARM: Fix issue with m5.fast and ARM 2010-06-03 12:20:49 -04:00
Ali Saidi
5268067f14 ARM: Fix SPEC2000 benchmarks in SE mode. With this patch all
Spec2k benchmarks seem to run with atomic or timing mode simple
CPUs. Fixed up some constants, handling of 64 bit arguments,
and marked a few more syscalls ignoreFunc.
2010-06-02 12:58:18 -05:00