gem5/src/arch
Ali Saidi 5268067f14 ARM: Fix SPEC2000 benchmarks in SE mode. With this patch all
Spec2k benchmarks seem to run with atomic or timing mode simple
CPUs. Fixed up some constants, handling of 64 bit arguments,
and marked a few more syscalls ignoreFunc.
2010-06-02 12:58:18 -05:00
..
alpha tick: rename Clock namespace to SimClock 2010-04-15 16:24:12 -07:00
arm ARM: Fix SPEC2000 benchmarks in SE mode. With this patch all 2010-06-02 12:58:18 -05:00
mips tick: rename Clock namespace to SimClock 2010-04-15 16:24:12 -07:00
power cpu: fix exec tracing memory corruption bug 2010-03-23 08:50:57 -07:00
sparc SPARC: Implement the version of movcc that uses the fp condition codes. 2010-05-14 14:22:51 -07:00
x86 x86: put back code that I accidentally deleted 2010-05-25 20:15:44 -07:00
isa_parser.py ARM: Fix custom writer/reader code for non indexed operands. 2010-06-02 12:57:59 -05:00
micro_asm.py scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access 2009-09-22 15:24:16 -07:00
micro_asm_test.py Add a second section to make sure the ROM is extended properly. 2007-05-31 22:21:21 +00:00
SConscript scons: import ply to work around scons sys.path weirdness 2010-03-10 15:39:34 -08:00