Commit graph

3888 commits

Author SHA1 Message Date
Nathan Binkert
cf72942506 Move time forward to Jan 1, 2009 and update stats
--HG--
extra : convert_revision : 9398362237443dc659f423a342bd27c923e90aea
2007-01-25 19:14:05 -05:00
Nathan Binkert
1c2949a2ff Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.pool:/y/binkertn/research/m5/rtc

--HG--
extra : convert_revision : 65ddda89f38c5fa874722c20e5d82ed1bb4e12d9
2007-01-25 15:00:04 -05:00
Nathan Binkert
73dd0ea357 Instead of passing an int to represent time between python and C++
pass the tuple of python's struct_time and interpret that.
Fixes a problem where the local timezone leaked into the time
calculation.  Also fix things so that the unix, python, and RTC
data sheets all get the right time.  Provide both years since 1900
and BCD two digit year.
Put the date back at 1/1/2006 for now.

--HG--
extra : convert_revision : 473244572f468de2cb579a3dd7ae296a6f81f5d7
2007-01-25 14:59:41 -05:00
Ali Saidi
8561c8366c fix smul and sdiv to sign extend, and handle overflow/underflow corretly
Only allow writing/reading of 32 bits of Y
Only allow writing/reading 32 bits of pc when pstate.am
Put any loaded data on the first half of a micro-op in uReg0 so it can't
overwrite the register we are using for address calculation
only erase a entry from the lookup table if it's valid
Put in a temporary check to make sure that lookup table and tlb array stay in sync
if we are interrupted in the middle of a mico-op, reset the micropc/nexpc
so we start  on the first part of it when we come back

src/arch/sparc/isa/decoder.isa:
    fix smul and sdiv to sign extend, and handle overflow/underflow corretly
    Only allow writing/reading of 32 bits of Y
    Only allow writing/reading 32 bits of pc when pstate.am
    Put any loaded data on the first half of a micro-op in uReg0 so it can't
    overwrite the register we are using for address calculation
src/arch/sparc/isa/formats/mem/blockmem.isa:
    Put any loaded data on the first half of a micro-op in uReg0 so it can't
    overwrite the register we are using for address calculation
src/arch/sparc/isa/includes.isa:
    Use limits for 32bit underflow/overflow detection
src/arch/sparc/tlb.cc:
    only erase a entry from the lookup table if it's valid
    Put in a temporary check to make sure that lookup table and tlb array stay in sync
src/arch/sparc/tlb_map.hh:
    add a print function to dump the tlb lookup table
src/cpu/simple/base.cc:
    if we are interrupted in the middle of a mico-op, reset the micropc/nexpc
    so we start  on the first part of it when we come back

--HG--
extra : convert_revision : 50a23837fd888393a5c2aa35cbd1abeebb7f55d4
2007-01-25 13:43:46 -05:00
Ali Saidi
4301e4cd08 use pstate.am to mask off PC/NPC where it needs to +be
check writability of tlb cache entry before using
update tagaccess in places I forgot to
move the tlb privileged test up since it is higher priority

src/arch/sparc/faults.cc:
    save only 32 bits of PC/NPC if Pstate.am is set
src/arch/sparc/isa/decoder.isa:
    return only 32 bits of PC/NPC if Pstate.am is set
    increment cleanwin correctly
src/arch/sparc/tlb.cc:
    check writability of cache entry
    update tagaccess in a few more places
    move the privileged test up since it is higher priority
src/cpu/exetrace.cc:
    mask off upper bits of pc if pstate.am is set before comparing to legion

--HG--
extra : convert_revision : 02a51c141ee3f9a2600c28eac018ea7216f3655c
2007-01-23 15:50:03 -05:00
Ali Saidi
60eaa03d72 fix compiling on x86/Solaris
--HG--
extra : convert_revision : f7d21fc277dd7172c244d83fb012883dc8b67895
2007-01-22 21:57:01 -05:00
Ali Saidi
5f662d451e clean up fault code a little bit
simplify and make complete some asi checks
implement all the twin asis and remove panic checks on their use
soft int is supported, so we don't need to print writes to it

src/arch/sparc/asi.cc:
    make AsiIsLittle() be all the little asis.
    Speed up AsiIsTwin() a bit
src/arch/sparc/faults.cc:
    clean up the do*Fault code.... Make it work like legion, in particular
    pstate.priv is left alone, not set to 0 like the spec says
src/arch/sparc/isa/decoder.isa:
    implement some more twin ASIs
src/arch/sparc/tlb.cc:
    All the twin asis are implemented, no need to say their not supported anymore
src/arch/sparc/ua2005.cc:
    softint is supported now, no more need to

--HG--
extra : convert_revision : aef2a1b93719235edff830a17a8ec52f23ec9f8b
2007-01-22 21:55:43 -05:00
Ali Saidi
3011fc6311 we decided to check for .interp instead of .dynamic
--HG--
extra : convert_revision : 4f5c7f9c7653e1e9ebbd488c07426d9f944bb25f
2007-01-22 21:45:29 -05:00
Ali Saidi
ddab4d756a Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 21e1bfa49a933f3b39bd2e7bcd873428f9d01a1b
2007-01-22 16:17:11 -05:00
Ali Saidi
5c1d631f36 check if an executable is dynamic and die if it is
Only implemented for ELf. Someone might want to implement it for ecoff and some point

src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
    add a function to check if an executable is dynamic
src/sim/process.cc:
    check if an executable is dynamic and die if it is

--HG--
extra : convert_revision : 830b1b50b08a5abaf895ce6251bbc702c986eebf
2007-01-22 16:14:06 -05:00
Ali Saidi
e347b49a4e use writeTagAccess() function to unify writing of Tag access registers
Fix extracting of secondary context to shove into tag access register
properly sign extend va from 59 bits to 63 (SPARC VA hole)

--HG--
extra : convert_revision : 5d0c2b4db63338c31b2d29b4bb68f39e1d4f4c7b
2007-01-22 16:11:49 -05:00
Ali Saidi
a7072c19db make sure that page bits of VA on tlb insert are 0
--HG--
extra : convert_revision : f04af884687e9b8631e910cf62cd4a58d035c744
2007-01-21 20:02:41 -05:00
Ali Saidi
3af3610c62 add dumb time of day device
--HG--
extra : convert_revision : 52e51ff49f7ed73065f04707ded06dc7254292c4
2007-01-21 18:04:40 -05:00
Ali Saidi
d8eeb2e0ff fix InterruptLevel code to return the correct level
(the bit positition that is set in softint)

--HG--
extra : convert_revision : ba0e1f4ec1f74aac64c3f9bb7eb1b771e17b013a
2007-01-20 23:12:32 -05:00
Ali Saidi
57d11578cf atually set all 64 bits of the retun value to 0
--HG--
extra : convert_revision : 77bfdf07a49d41a2392f429fdc632c1461ac504c
2007-01-20 23:10:43 -05:00
Ali Saidi
95e4a51c6c fix flushw implementation
--HG--
extra : convert_revision : 136b2bddc7cb70cde30e930ad3a13bd56c7162e1
2007-01-20 23:09:28 -05:00
Ali Saidi
ccd67ce44f Rearange tlb code to remove some duplicate
Sparc error register should return ull(0) since it's 64 bits
Fix PS1 pointer creation to use the ps1 page size rather than ps0

--HG--
extra : convert_revision : fb4ef4b90270c8db676ffe53578acfa3c244526e
2007-01-20 12:37:02 -05:00
Ali Saidi
6e0f1c6062 Spill and Fill handlers are actually n*4 + the start address
--HG--
extra : convert_revision : a42f01a84e4b7ba9e6029df50e1612d410a8ba22
2007-01-20 12:34:00 -05:00
Lisa Hsu
01c959aeaf Merge zed.eecs.umich.edu:/.automount/zeep/z/saidi/work/m5.newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5

--HG--
extra : convert_revision : 9b8567bb775ed6fcc30096f1ab4cc37058bc7376
2007-01-19 21:34:21 -05:00
Lisa Hsu
f1aeaf7ceb some hstick and hintp changes.
src/arch/sparc/interrupts.hh:
    condition hstick matches on HINTP
src/arch/sparc/miscregfile.cc:
    implement HINTP
src/arch/sparc/ua2005.cc:
    don't post interrupt unless it is enabled.

--HG--
extra : convert_revision : f71d1c1d9fd1a898ddafd5a885c3a8d5c75e8ff0
2007-01-19 21:33:36 -05:00
Ali Saidi
ae0d8d1681 Allow ASI_LDTX_REAL
--HG--
extra : convert_revision : ba1af012ab8ac61a25058977cb7ec511eb2cf3cb
2007-01-17 18:36:12 -05:00
Ali Saidi
c8a2d602b1 do a linear search for matching tlb entries instead of using map because you could be mapping a larger page that intersects many
fix for lookup table to keep it consistant with tlb on a replace of a specific entry

--HG--
extra : convert_revision : 5a14fbcdcfc13156c63fa41ddeca474660143b32
2007-01-17 17:59:22 -05:00
Ali Saidi
8173a05eaf Implement reading writing of sync fault status register and address register
--HG--
extra : convert_revision : c2f60e49683446bcc3afdf911da172de0422b8ad
2007-01-17 13:09:26 -05:00
Ali Saidi
64528df38d In the case that we generate a fault (e.g. a tlb miss) on a microcoded instruction set curMacroStaticInst to null
This way we'll jump immediately to the handler

--HG--
extra : convert_revision : 36218d3a5c2342337e66e1229ea2219533efd41e
2007-01-16 19:12:33 -05:00
Ali Saidi
8d75e4ac3f Don't add symbols for loaded files to symbol table since they are pretty much meaningless with all the copying that goes on
--HG--
extra : convert_revision : 4d2c1bb72c0344d78d9c3d5958feb3de247102a0
2007-01-16 19:09:27 -05:00
Ali Saidi
d6c92cdb3c Fix legion lock code a bit so that if we jump out of a micro coded instruction (because of a fault on the first op) we don't lose sync with legion
Only print TLB if there is a tlb difference

--HG--
extra : convert_revision : f3baf667ca466d6b8efcaccd186ecec14498229d
2007-01-16 19:08:21 -05:00
Ali Saidi
0584d5bd6c In the case of ASI_P or ASI_LDTX_P set primary and skip the other checks
--HG--
extra : convert_revision : e7b21c56eadf4603ab03364741b00c9689492423
2007-01-16 19:06:33 -05:00
Ali Saidi
ecfd628ecd Modify ISA and staticInst to support a IsFirstMicroOp flag
Increment instruction count on first micro-op instead of last

src/arch/sparc/isa/decoder.isa:
    Implement a twin load for ASI_LDTX_P(0xe2)
src/arch/sparc/isa/formats/mem/blockmem.isa:
    set the new flag IsFirstMicroOp when needed
src/cpu/simple/atomic.cc:
    Increment instruction count on first micro-op instead of last (because if we take a fault on a micro coded instruction it should be counted twice acording to legion)
src/cpu/static_inst.hh:
    Add IsFirstMicroop flag to static insts

--HG--
extra : convert_revision : 02bea93d38c03bbafe4570665eb4c01c11caa2fc
2007-01-16 19:06:05 -05:00
Lisa Hsu
5c9cbdbb45 Merge zed.eecs.umich.edu:/z/hsul/work/sparc/ali.m5
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

src/arch/sparc/ua2005.cc:
    hand merge between ali and me.

--HG--
extra : convert_revision : 810d63fb484ab26fc30f8130ef32390ba149b267
2007-01-11 09:48:15 -05:00
Lisa Hsu
42535f5f53 ua2005.cc:
formatting/indentation for case statements

src/arch/sparc/ua2005.cc:
    formatting/indentation for case statements

--HG--
extra : convert_revision : aeb7d0274d8d22db3fa56aabbb8ab8f5371a32ff
2007-01-11 09:41:34 -05:00
Lisa Hsu
9f75c1c58f ua2005.cc:
i SWEAR i committed this already, but apparently i didnt.  ust start using HPSTATE::hpriv, etc. to access bitfields.

src/arch/sparc/ua2005.cc:
    i SWEAR i committed this already, but apparently i didnt.  ust start using HPSTATE::hpriv, etc. to access bitfields.

--HG--
extra : convert_revision : e66fac9c63088c0fc1a62bd0fac92df305beadff
2007-01-11 09:29:03 -05:00
Lisa Hsu
d939060ec6 Add Trap Level Zero to interrupts, remove some unreachable code that I forgot to remove last time.
--HG--
extra : convert_revision : 74c4c4591be5a66c21077a6fc5f3f60b0ee9bcc1
2007-01-11 09:18:31 -05:00
Ali Saidi
9d04510869 bug fixes to get us to 145m instructions
src/arch/sparc/intregfile.cc:
    some checks to make sure that the cwp and global register flattening stuff is working. These things have caught a couple of bugs so I think it would be good to keep them around at least for now
src/arch/sparc/isa/decoder.isa:
    fix smul instruction to write Y correctly
src/arch/sparc/miscregfile.cc:
    legion always returns du and dl set, so we need to emulate that for now at least

--HG--
extra : convert_revision : 82f9276340888f1e43071c69504486efdcfdb3a8
2007-01-10 22:19:13 -05:00
Ali Saidi
28a83c6d1c quiet/remove some warnings
fix implementation of cwp manipulation
implement PS0 and PS1 IMMU asis

src/arch/sparc/miscregfile.cc:
    get rid of some warnings
    fix implementation of setting cwp to saturate cwp since it appears the os sets it to a large value to see how many there actually are
src/arch/sparc/tlb.cc:
    implement PS0 and PS1 IMMU access ASIs
src/arch/sparc/ua2005.cc:
    make warning less verbose

--HG--
extra : convert_revision : 442b65dfc41ebc32b2ef0e6b80da94eee3be9cd3
2007-01-09 22:20:38 -05:00
Ali Saidi
7933aade85 add memory mapped disk device
configs/common/FSConfig.py:
src/python/m5/objects/T1000.py:
    add configuration for memory mapped disk
src/dev/sparc/SConscript:
    add memory mapped disk to sconscript

--HG--
extra : convert_revision : d8df4a455cf48000042d0ff93a274985f4dbe905
2007-01-09 22:16:49 -05:00
Lisa Hsu
0d7282d7ab pagetable.hh:
small fix so ALPHA_FS will build on macs
interrupts.hh:
small fix for alpha compile

src/arch/alpha/interrupts.hh:
    small fix for alpha compile
src/arch/alpha/pagetable.hh:
    small fix so ALPHA_FS will build on macs

--HG--
extra : convert_revision : 5fdbc68caa706d652b51807ac8f6bf58bcf72bdc
2007-01-08 20:50:45 -05:00
Lisa Hsu
032ea9b2db the way i understand it, interrupts in m5 is a little bloated. the usage of CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in.
src/arch/sparc/interrupts.hh:
    fill in how we do interrupts on sparc a little bit.

    1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU.
    2) fill in getInterrupts() a little bit.

    also, update the bitfield access to be HPSTATE::hpriv, etc.
src/arch/sparc/ua2005.cc:
    1) update formatting
    2) change the way interrupts are done to use the new way to tickle the CPU.
src/cpu/base.cc:
src/cpu/base.hh:
    overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value.

--HG--
extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5
2007-01-08 18:18:28 -05:00
Lisa Hsu
b45219e7ae some formatting changes, and update how I do bitfields for HPSTATE and PSTATE to avoid name confusion.
src/arch/sparc/faults.cc:
    1) s/Resumeable/Resumable/gc
    2) s/if(/if (/gc
    3) keep variables lowercase
    4) change the way fields are accessed - instead of hard coding bitvectors, use masks (like HPSTATE::hpriv).
src/arch/sparc/faults.hh:
    s/Resumeable/Resumable/
src/arch/sparc/isa_traits.hh:
    This is unused and unnecessary.
src/arch/sparc/miscregfile.hh:
    add bitfield masks for some important ASRs (HPSTATE, PSTATE).

--HG--
extra : convert_revision : f0ffaf48de298758685266dfb90f43aff42e0a2c
2007-01-08 18:07:17 -05:00
Ali Saidi
a8b2d66661 change when legion-lock causes the simulation to die. It now happens after two consuctive differences since we compare stuff
at slightly different times interrupts are seen the cycle before they happen in m5 so the pc gets changed early.

--HG--
extra : convert_revision : f237363eababb2aad67e5b41670cf40be048a042
2007-01-08 17:11:10 -05:00
Ali Saidi
2f4239a685 fix softint and partially implement hstick interrupts need to figure out how to do the acutal interrupting still
src/arch/sparc/miscregfile.cc:
    fix softint and fprs in miscregfile

--HG--
extra : convert_revision : cf98bd9c172e20f328f18e07dd05f63f37f14c87
2007-01-08 17:09:48 -05:00
Ali Saidi
4a8078192d set the softint appropriately on an timer compare interrupt
there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly

src/arch/sparc/faults.cc:
    there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly
src/arch/sparc/faults.hh:
    correct protection defines
src/arch/sparc/ua2005.cc:
    set the softint appropriately on an timer compare interrupt

--HG--
extra : convert_revision : f41c10ec78db973b3f856c70b58a17f83b60bbe2
2007-01-05 15:04:17 -05:00
Ali Saidi
b0f11f8f81 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : e8ac13e1222796ab362fabb9b19694682538da29
2007-01-04 20:22:56 -05:00
Ali Saidi
b46aa88435 Fix stick compare to work correctly and set checkInterrupts to true at the appropriate time
turn warnings into dprintfs

src/arch/sparc/miscregfile.cc:
    turn dprintfn into dprintfs

--HG--
extra : convert_revision : cd313e9037c8f040d837de4c7ddbcf98534e60ad
2007-01-04 20:22:45 -05:00
Nathan Binkert
e6b4fed75d set __name__ in the root m5 script to __m5_main__ so we can
tell if the script is run from m5 as the m5 script

--HG--
extra : convert_revision : 06f646cbb8c82444ef345115aa49324a4d3a2c9f
2007-01-03 10:16:22 -08:00
Nathan Binkert
e9a395c2ce Formatting
--HG--
extra : convert_revision : bf1eae73995f772a4343c8ebcb254818eeb5d949
2007-01-03 10:13:45 -08:00
Nathan Binkert
fc45d42d01 Add 'Time' as a parameter type that can accept various
formats for time (strings, datetime objects, etc.)
Advance system time to 1/1/2009
Clean up time management code a little bit

--HG--
extra : convert_revision : 28ebecc7ea6b12f4345c77a9a6b4bdf2e752c4f8
2007-01-03 10:12:55 -08:00
Kevin Lim
7d7f3d0e99 Fix up previous commit to proper logic.
src/cpu/o3/commit_impl.hh:
    Oops, changed the logic a little bit.  Fix it up to how it used to be.

--HG--
extra : convert_revision : df7f69b0997207b611374c3c92880f3a405e88be
2006-12-30 13:21:25 -05:00
Nathan Binkert
f6aa2ed47b Merge zizzer.eecs.umich.edu:/bk/newmem
into  iceaxe.:/Volumes/work/m5/incoming

--HG--
extra : convert_revision : dad5311afaaf40c1378017514c8b3f73852f13f5
2006-12-29 16:58:08 -08:00
Nathan Binkert
81e0ac3000 Formatting
--HG--
extra : convert_revision : f5a940a8b9aaba0703781b398cf29be581907c21
2006-12-29 16:57:45 -08:00
Ali Saidi
b48a8fb347 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : afd4266bd494bb8f127c06985f343219ded4f637
2006-12-27 14:38:22 -05:00