SConstruct:
Add check to see if we need to include libsocket
src/arch/sparc/floatregfile.cc:
src/arch/sparc/intregfile.cc:
use memset rather than bzero and include the appropriate headerfile
src/base/pollevent.cc:
If we're compling under solaris we need sys/file.h
src/base/random.cc:
src/base/random.hh:
solaris doesn't have random(), so use rint with the correct rounding mode
if we're compiling on solaris
src/base/stats/flags.hh:
u_int32_t??
src/base/time.hh:
grab the timersub() define from freebsd since it doesn't exist in solaris
src/cpu/inst_seq.hh:
we don't need to include stdint here
src/sim/byteswap.hh:
the method to detect endianness on Solaris is a little more complex...
--HG--
extra : convert_revision : 6b7db0e900e7bccfc250d65c125065f27280dda1
src/arch/sparc/faults.cc:
Moved some code here from miscregfile.cc
src/arch/sparc/miscregfile.cc:
Moved code from here to faults.cc, and merged (read|set)MiscRegWithEffect and it's FS version from ua2005.cc
src/arch/sparc/miscregfile.hh:
readFSRegWithEffect is no longer a seperate function, and is instead done in the main readRegWith Effect.
--HG--
extra : convert_revision : 0b45f0f78e83929b32ddd2f443c8b1dbf9bc04fb
src/arch/sparc/isa/decoder.isa:
Fix up the casa and casxa instructions.
src/arch/sparc/isa/formats/formats.isa:
This is handled in loadstore.isa now
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
Renamed doSplitExecute to doDualSplitExecute. This differentiates between the version that does both a register and immediate version, and one that just does a register version.
src/arch/sparc/isa/formats/mem/mem.isa:
The cas format is handled in loadstore.isa as well now.
src/arch/sparc/isa/formats/mem/util.isa:
Reorganized things a bit to better support cas
--HG--
extra : convert_revision : 12411e89e763287e52f9825bf7a417b263c1037f
src/arch/sparc/isa/formats/priv.isa:
Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated.
src/arch/sparc/isa/operands.isa:
Added an Hpstate operand, and adjusted the numbering.
--HG--
extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart.
--HG--
extra : convert_revision : 59adb96570cce86f373fbc2c3e4c05abe1742d3b
src/arch/sparc/isa/formats/blockmem.isa:
Several small and medium bug fixes.
src/cpu/simple/base.cc:
Fixed a few compiler errors and made sure the next micro pc is set to 1 to prevent the first microop from executing twice. Also fixed a fetching bug.
src/cpu/thread_state.cc:
Made sure the microPC and nextMicroPC are initialized properly.
--HG--
extra : convert_revision : a0fc8aa18d1ade916f17c557181a793c6108a8af
src/arch/sparc/isa/base.isa:
src/arch/sparc/isa/formats/micro.isa:
Switch MachInst to ExtMachInst so that the EXT_ASI field is available to the instructions.
src/arch/sparc/utility.hh:
Made sure EXT_ASI was set to the appropriate ASI value whether or not the asi register was used.
--HG--
extra : convert_revision : cc4363dfe7da81969959cec9d5ad48528edeb8ce
src/arch/isa_parser.py:
Changed the way the extra template parameters are specified. MIPS might need to be adjusted.
src/arch/sparc/isa/decoder.isa:
Changed how Frd_N was set up.
src/arch/sparc/isa/formats/blockmem.isa:
Fixed up handling of block memory operations
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem.isa:
src/arch/sparc/isa/formats/priv.isa:
Fix up extra template parameters.
--HG--
extra : convert_revision : ebf850d192193521bb84ca36b577051f74338d23
src/arch/sparc/isa/bitfields.isa:
Added a field to retrieve the asi from the ExtMachInst
src/arch/sparc/isa/decoder.isa:
Fixed up how the size of memory operations where handled, and use the new EXT_ASI bit field.
src/arch/sparc/isa/formats.isa:
add includes for the new formats.
src/arch/sparc/isa/formats/basic.isa:
Add a template for BasicDecodeWithMnemonic which is needed by the unimp format.
src/arch/sparc/isa/formats/mem.isa:
Change around the memory format to figure out the memory access width on its own.
src/arch/sparc/isa/operands.isa:
Added support for the operands of block loads/stores which are offset from Frd.
src/arch/sparc/utility.hh:
Encoded the ASI into the ExtMachInst
--HG--
extra : convert_revision : 5c6026a07e3a919e738d27f78beb0faf6b060643
and PhysicalMemory. *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.
src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
--HG--
extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
src/arch/sparc/SConscript:
Added a file that implements ASI utility functions. These don't go in utility.hh because they aren't supposed to be part of the generic ISA interface.
src/arch/sparc/asi.hh:
Fixed up some mistranscriptions, and added function prototypes for some ASI utility functions.
src/arch/sparc/asi.cc:
Implementation of some ASI utility functions.
--HG--
extra : convert_revision : 8021007027b13e91cc66908029470da49a8ca11f
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/process.hh:
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/process.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/linux/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/solaris/process.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters.
src/kern/tru64/tru64.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters. Also fit tru64 in with the new way to handle stat calls.
--HG--
extra : convert_revision : 0198b838e5c09a730065dc6f018738145bc96269
Added in the filename parameter which is provided for the user space linker.
Fix the ordering and alignment of stack elements.
Made mmap start with the address it has been seen starting with "in the wild"
--HG--
extra : convert_revision : 8734753145f59a6cb433e4f92f43cb28a44b56d4
1. alignaddr wrote it's address to a floating point register rather than a gpr.
2. sethi was sign extending it's immediate value.
--HG--
extra : convert_revision : 9aa30a6485bc4cba916367973b986d439b7c7588
Nate needs to fix sinic builder stuff
Gabe needs to verify my fixes to decoder.isa
OPT/DEBUG compiles for ALPHA_FS, ALPHA_SE, MIPS_SE, SPARC_SE with this changeset
README:
Fix the swig version in the readme
src/SConscript:
remove sinic until nate fixes the builder crap for it
src/arch/alpha/system.hh:
src/arch/mips/isa/includes.isa:
src/arch/sparc/isa/decoder.isa:
src/base/stats/visit.cc:
src/base/timebuf.hh:
src/dev/ide_disk.cc:
src/dev/sinic.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr_queue.cc:
src/mem/packet.hh:
src/mem/request.hh:
src/sim/builder.hh:
src/sim/system.hh:
fixes for gcc 4.1
--HG--
extra : convert_revision : 3775427c0047b282574d4831dd602c96cac3ba17
src/arch/sparc/process.cc:
All of the auxilliary vectors are now set like they are in the linux elf loader. This code should probably be moved to arch/sparc/linux/process.cc somehow.
--HG--
extra : convert_revision : 4a90cacf70b1032cad3f18b0f833a6df8237e0de
src/arch/sparc/isa/operands.isa:
Added the GSR register as a control register
--HG--
extra : convert_revision : 11ff4016d5c72468dd2daeba3a6105d4e84220ce
src/arch/sparc/isa/decoder.isa:
fixed subc, subccc, added decoding for impdep1 to fit with ua2005, and started work on floating point.
src/arch/sparc/isa/operands.isa:
Added in floating point operands, and changed the numbering of operands.
src/arch/sparc/regfile.hh:
Fixed some memory errors related to floating point.
--HG--
extra : convert_revision : fa0aef2021a5cf99f175fceeb533fe63eb5f805c
update scripts acordingly
configs/test/SysPaths.py:
new syspaths from nate, this one allows you to set script, binary, and disk paths like
system.dir = 'aouaou' in your script
configs/test/fs.py:
update for system mem_mode
Put small checkpoint example
Make clock 1THz
configs/test/test.py:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/system.cc:
src/arch/alpha/tru64/system.cc:
src/arch/sparc/system.cc:
src/python/m5/objects/System.py:
src/sim/system.cc:
src/sim/system.hh:
update for system mem_mode
src/dev/io_device.cc:
Use time returned from sendAtomic to delay
--HG--
extra : convert_revision : 67eedb3c84ab2584613faf88a534e793926fc92f
src/cpu/simple/base.cc:
add syscall emulation page table fault so we can allocate more stack pages
FaultBase::invoke will do this, we don't need to do it here
src/sim/faults.hh:
I have no idea why this #if was there... gone
src/sim/process.cc:
make stack_min actually be the current minimum
--HG--
extra : convert_revision : 9786b39f2747b94654a5d77c74243cd20503add4
