and breaks it into a separate EA and MemAccess templated
from how the Alpha ARch. was coded to do the same thing.
arch/mips/isa/bitfields.isa:
comment change
arch/mips/isa/decoder.isa:
re-structuring of load/store instruction definitions
arch/mips/isa/formats/mem.isa:
Define LoadMemory & Store Memory formats
Use style of formatting & base class similar to what was used for ALPHA
arch/mips/isa/formats/util.isa:
Insert LoadStoreBase function here from alpha/arch/isa/mem.isa
arch/mips/isa/operands.isa:
change shw->sh and uhw->uh
--HG--
extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a
Redo format for Branches and Jumps ( Must update NNPC not NPC )
Now all branches and jumps look like they auto-generate correctly from isa_parser.py!!!
arch/mips/isa/decoder.isa:
Support for All Jump Instructions ..
arch/mips/isa/formats/branch.isa:
Redo format for Branches and Jumps ( Must update NNPC not NPC )
arch/mips/isa/formats/util.isa:
define clear_exe_inst_hazards for later use
--HG--
extra : convert_revision : 63618ed12ee6ed94c47d29619cc1cab2cbaf5cda
Edits to the CPU model may still need to be made to handle branch likely insts...
arch/isa_parser.py:
add a NNPC operand ...
arch/mips/isa/base.isa:
change SPARC to MIPS
arch/mips/isa/decoder.isa:
typo < to >=
arch/mips/isa/formats/basic.isa:
spacing
arch/mips/isa/formats/branch.isa:
add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
support for NNPC and R31
arch/mips/isa_traits.hh:
NNPC Addr variable
--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
Now, must create g++ compilable code ...
arch/mips/isa/decoder.isa:
missing a '}' ... edited a few instruction decodings ...
arch/mips/isa/formats.isa:
rearranged #include
arch/mips/isa/formats/branch.isa:
add Branch Likely and Unconditional format
arch/mips/isa/formats/int.isa:
move OperateNopCheckDecode template to another file ...
arch/mips/isa/formats/noop.isa:
change Alpha to Mips in noop.isa
--HG--
extra : convert_revision : 4bf955fa6dffbbc99fb95fee7878f691e3df5424
arch/mips/isa/decoder.isa:
CondBranch format split up into Branch & BranchLikely formats
arch/mips/isa/formats.isa:
include util.isa
arch/mips/isa/formats/branch.isa:
erroneous 'e' at top of code
arch/mips/isa/formats/util.isa:
util.isa
--HG--
extra : convert_revision : 4fc44a05e2838749e66cd70f210e8a718b34cbf3
arch/alpha/main.isa to test my files ...
arch/mips/isa/operands.isa:
use sd and ud instead of sdw and udw
--HG--
extra : convert_revision : d66f3fd2c4a4d70e6015f0f1643c400cdfe73055
arch/mips/isa/decoder.isa:
Code for di,ei,seb,seh,clz,and clo ....
Every instruction has a format now (of course these are initial formats are still subject to change!)
arch/mips/isa/formats/branch.isa:
Format Branch in MIPS similar to Alpha Format
--HG--
extra : convert_revision : 2118a1d9668610b1e9f1dea66d878b7b36c1ac7e
The extra class is needed because of the necessisty of an immediate member variable.
Also, added some 'very modest' python code to choose between the IntOp and
the IntImmOp based on the instruction name ...
--HG--
extra : convert_revision : f109c12418202a99b40e270360134e8335739836
arch/mips/isa/formats/int.format:
Looks like Integer Ops with Immediates may not need their own separate class because all those instructions are distinct from
their reg-reg counterparts
--HG--
rename : arch/mips/isa/bitfields.def => arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.def => arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats.def => arch/mips/isa/formats.isa
rename : arch/mips/isa/includes.h => arch/mips/isa/includes.isa
rename : arch/mips/isa/operands.def => arch/mips/isa/operands.isa
extra : convert_revision : 8e354b4232b28c0264d98d333d55ef8b5a6589cc
