a48c24b61e
Edits to the CPU model may still need to be made to handle branch likely insts...
arch/isa_parser.py:
add a NNPC operand ...
arch/mips/isa/base.isa:
change SPARC to MIPS
arch/mips/isa/decoder.isa:
typo < to >=
arch/mips/isa/formats/basic.isa:
spacing
arch/mips/isa/formats/branch.isa:
add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
support for NNPC and R31
arch/mips/isa_traits.hh:
NNPC Addr variable
--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
|
||
|---|---|---|
| .. | ||
| basic.isa | ||
| branch.isa | ||
| fp.isa | ||
| int.isa | ||
| mem.isa | ||
| noop.isa | ||
| tlbop.isa | ||
| trap.isa | ||
| unimp.isa | ||
| unknown.isa | ||
| util.isa | ||