Commit graph

3201 commits

Author SHA1 Message Date
Gabe Black
ab44417282 Fixes to the bus, and added fields to the packet.
src/mem/bus.cc:
    Put back the check to see if the bus is busy. Also, populate the fields in the packet to indicate when the first word and the entire packet will be delivered.
src/mem/bus.hh:
    Remove the occupyBus function.
src/mem/packet.hh:
    Added fields to the packet to indicate when the first chunk of a packet arrives, and when the entire packet arrives.

--HG--
extra : convert_revision : cfc7670a33913d48a04d02c6d2448290a51f2d3c
2006-10-09 23:24:21 -04:00
Gabe Black
5448517da4 updated reference output
--HG--
extra : convert_revision : daf11630290c7a84d63bf37cafa44210861c4bf2
2006-10-09 19:55:49 -04:00
Gabe Black
843888c489 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

--HG--
extra : convert_revision : 2adde42edead2cedeeba60cc0d2697a2d58682be
2006-10-09 19:35:53 -04:00
Ron Dreslinski
9356bcda7b Fix a typo preventing compilation
--HG--
extra : convert_revision : 9158d81231cd1d083393576744ce80afd0b74867
2006-10-09 19:20:28 -04:00
Ron Dreslinski
e03b9c9939 Fix how upgrades work.
Remove some dead code.

src/mem/cache/cache_impl.hh:
    Upgrades don't need a response.
    Moved satisfied check into bus so removed some dead code.
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/packet.hh:
    Upgrades don't require a response

--HG--
extra : convert_revision : dee0440ff19ba4c9e51bf9a47a5b0991265cfc1d
2006-10-09 19:15:24 -04:00
Ron Dreslinski
13ac9a419d One step closet to having NACK's work.
src/cpu/memtest/memtest.cc:
    Fix functional return path
src/cpu/memtest/memtest.hh:
    Add snoop ranges in
src/mem/cache/base_cache.cc:
    Properly signal NACKED
src/mem/cache/cache_impl.hh:
    Catch nacked packet and panic for now

--HG--
extra : convert_revision : 59a64e82254dfa206681c5f987e6939167754d67
2006-10-09 18:52:20 -04:00
Gabe Black
a23c6a7193 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

--HG--
extra : convert_revision : 8267487b935eaf11665841ace3a5c664751b53b0
2006-10-09 18:19:35 -04:00
Gabe Black
187dcb18bf Potentially functional partially timed bandwidth limitted bus model.
src/mem/bus.cc:
    Fixes to the previous hand merging, and put the snooping back into recvTiming and out of it's own function.
src/mem/bus.hh:
    Put snooping back into recvTiming and not in it's own function.

--HG--
extra : convert_revision : fd031b7e6051a5be07ed6926454fde73b1739dc6
2006-10-09 18:12:45 -04:00
Ron Dreslinski
727dea78c4 Update configs for cpu_id
tests/configs/o3-timing-mp.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
    Update config for cpu_id

--HG--
extra : convert_revision : 32a1971997920473164ba12f2b121cb640bad7ac
2006-10-09 17:31:58 -04:00
Ron Dreslinski
c4dba7a8ed Fix a typo in the printf
--HG--
extra : convert_revision : bfa8ffae0a9bef25ceca168ff376ba816abf23f3
2006-10-09 17:30:54 -04:00
Ron Dreslinski
094c6de663 Multiprogrammed workload, need to generate ref's for it yet. But Nate wanted the config.
Not sure on the naming convention for tests.

--HG--
extra : convert_revision : 052c2fc95dc7e2bbd78d4a177600d7ec2a530a4c
2006-10-09 17:25:43 -04:00
Ron Dreslinski
fd27c229b6 Fix a bitwise operation that was accidentally a logical operation.
--HG--
extra : convert_revision : 30f64bcb6bea47fd8cd6d77b0df17eff04dbbad0
2006-10-09 17:18:34 -04:00
Ron Dreslinski
b9fb4d4870 Make memtest work with 8 memtesters
src/mem/physical.cc:
    Update comment to match memtest use
src/python/m5/objects/PhysicalMemory.py:
    Make memtester have a way to connect functionally
tests/configs/memtest.py:
    Properly create 8 memtesters and connect them to the memory system

--HG--
extra : convert_revision : e5a2dd9c8918d58051b553b5c6a14785d48b34ca
2006-10-09 17:13:50 -04:00
Ron Dreslinski
d7c1557e7e Merge zizzer:/z/m5/Bitkeeper/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : b4cb1702ffa2fca298cfde47683cac019e1da900
2006-10-09 16:48:58 -04:00
Ron Dreslinski
45732376f6 Add more DPRINTF's fix a supply condition.
src/mem/cache/cache_impl.hh:
    Add more usefull DPRINTF's
    REmove the PC to get rid of asserts

--HG--
extra : convert_revision : 3f6d832b138d058dbe79bb5f42bd2db9c50b35b5
2006-10-09 16:47:55 -04:00
Ron Dreslinski
afce51d10a Set size properly on uncache accesses
Don't use the senderState after you get a succesful sendTiming.  Not guarnteed to be correct

src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.hh:
    Don't use the senderState after you get a succesful sendTiming.  Not guarnteed to be correct

--HG--
extra : convert_revision : 2e8e812bf7fd3ba2b4cba7f7173cb41862f761af
2006-10-09 16:37:02 -04:00
Ron Dreslinski
bc732b59fd Have cpus send snoop ranges
--HG--
extra : convert_revision : 2a1fba141e409ee1d7a0b69b5b21d236e3d4ce68
2006-10-09 01:04:37 -04:00
Ron Dreslinski
095d5991f5 Put a check in so people know not to create more than 8 memtesters.
--HG--
extra : convert_revision : 41ab297dc681b2601be1df33aba30c39f49466d8
2006-10-09 00:31:24 -04:00
Ron Dreslinski
95ca4f9d4a Merge zizzer:/z/m5/Bitkeeper/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : 77b06379a520dd91f124c0a543e30ec3a9cd1452
2006-10-09 00:28:26 -04:00
Ron Dreslinski
0087061681 Don't create a response if one isn't needed.
--HG--
extra : convert_revision : 37bd230f527f64eb12779157869aae9dcfdde7fd
2006-10-09 00:27:41 -04:00
Ron Dreslinski
4f93c43d34 Don't block responses even if the cache is blocked.
--HG--
extra : convert_revision : a1558eb55806b2a3e7e63249601df2c143e2235d
2006-10-09 00:27:03 -04:00
Ron Dreslinski
6c7ab02682 Update the Memtester, commit a config file/test for it.
src/cpu/SConscript:
    Add memtester to the compilation environment.
    Someone who knows this better should make the MemTest a cpu model parameter.

    For now attached with the build of o3 cpu.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
    Update Memtest for new mem system
src/python/m5/objects/MemTest.py:
    Update memtest python description

--HG--
extra : convert_revision : d6a63e08fda0975a7abfb23814a86a0caf53e482
2006-10-09 00:26:10 -04:00
Lisa Hsu
67a114fc29 add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N. the default checkpoint directory is the cwd.
so you can restore by a command line like this:

m5.opt fs.py --checkpoint_dir="/my/ckpt/dir" -c 3

configs/example/fs.py:
    add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N.

--HG--
extra : convert_revision : bf9c8d3265a3875cdfb6a878005baa7ae29af90d
2006-10-09 00:12:16 -04:00
Lisa Hsu
67c20dd9dd Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : a0775bf59ff7049b76917b1ab551bc28efd56b3d
2006-10-08 23:19:03 -04:00
Lisa Hsu
97c1f6eff7 post checkpoint restoration the bus ranges need to be re-initialized for ALL pci devs, not just ide.
src/dev/ide_ctrl.cc:
    this range change needs to be done for all pio devices, not just the ide.
src/dev/pcidev.cc:
    range change needs to be done at here, not in the ide_ctrl file.

--HG--
extra : convert_revision : 60c65c55e965b02d671dba7aa8793e5a81f40348
2006-10-08 23:18:19 -04:00
Lisa Hsu
d52117d1e3 add in serialization of AtomicSimpleCPU _status. This is needed because right now unserializing breaks an assert since CPU status is not saved. Kev says that this will break uniform serialization across CPUs since each type of CPU has its own "status" enum set. So, the repercussions are that if you serialize in this CPU, you must first unserialize in this CPU before switching to something else you want.
src/cpu/simple/atomic.cc:
    add in serialization of AtomicSimpleCPU _status.  Kev says that this will break uniform serialization across CPUs since each type of CPU has its own "status" enum set.  So, the repercussions are that if you serialize in this CPU, you must first unserialize in this CPU before switching to something else you want.

--HG--
extra : convert_revision : 7000f660aecea6fef712bf81853d9a7b90d625ee
2006-10-08 23:16:40 -04:00
Steve Reinhardt
a2bdddcc6f Merge zizzer.eecs.umich.edu:/bk/newmem
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : 755af6a54b309417afbc022544ee72f96bdac493
2006-10-08 19:11:19 -07:00
Steve Reinhardt
91c76278b9 Set cpu_id params (required by ll/sc code now).
--HG--
extra : convert_revision : e0f7ccbeccca191a8edb54494d2b4f9369e9914c
2006-10-08 19:11:06 -07:00
Lisa Hsu
ce6c752ede update for m5 base linux. (the last changes were for the latest m5hack, i.e. with nate's stuff in it).
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout:
    update for m5 base linux.

--HG--
extra : convert_revision : c78a1748bf8a0950450c29a7b96bb8735c1bb3d2
2006-10-08 22:05:34 -04:00
Steve Reinhardt
31f3f24214 Fixes for Port proxies and proxy parameters.
--HG--
extra : convert_revision : 76b16fe2926611bd1c12c8ad7392355ad30a5138
2006-10-08 18:26:59 -07:00
Ron Dreslinski
0a3e4d56e5 Update stats for functional path fix
--HG--
extra : convert_revision : 0f38abab28e7e44f1dc748c25938185651dd1b7d
2006-10-08 21:08:27 -04:00
Ron Dreslinski
4cfddc0d77 Make sure to propogate sendFunctional calls with functional not atomic.
src/mem/cache/cache_impl.hh:
    Fix a error case by putting a panic in.
    Make sure to propogate sendFunctional calls with functional not atomic.

--HG--
extra : convert_revision : 05d03f729a40cfa3ecb68bcba172eb560b24e897
2006-10-08 20:47:50 -04:00
Ron Dreslinski
5cb1840b31 Fixes for functional path.
If the cpu needs to update any state when it gets a functional write (LSQ??)
then that code needs to be written.

src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    CPU's can recieve functional accesses, they need to determine if they need to do anything with them.
src/mem/bus.cc:
src/mem/bus.hh:
    Make the fuctional path do the correct tye of snoop

--HG--
extra : convert_revision : 70d09f954b907a8aa9b8137579cd2b06e02ae2ff
2006-10-08 20:30:42 -04:00
Gabe Black
2df9053bb0 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

src/mem/bus.cc:
    Hand merged. Needs to be fixed

--HG--
extra : convert_revision : df03219ccfd18431cc726a063bd29d30554944a1
2006-10-08 19:14:09 -04:00
Ron Dreslinski
e65f0cef3c Only respond if the pkt needs a response.
Fix an issue with memory handling writebacks.

src/mem/cache/base_cache.hh:
src/mem/tport.cc:
    Only respond if the pkt needs a response.
src/mem/physical.cc:
    Make physical memory respond to writebacks, set satisfied for invalidates/upgrades.

--HG--
extra : convert_revision : 7601987a7923e54a6d1a168def4f8133d8de19fd
2006-10-08 19:05:48 -04:00
Ron Dreslinski
8a539a774f Merge zizzer:/z/m5/Bitkeeper/newmem
into  zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest

--HG--
extra : convert_revision : f3067efb7f3ff30158d541dfc52de4ea8edae576
2006-10-08 18:49:30 -04:00
Ron Dreslinski
1345183a89 Move away from using the statusChange function on snoops. Clean up snooping code in general.
--HG--
extra : convert_revision : 5a57bfd7742a212047fc32e8cae0dc602fdc915c
2006-10-08 18:48:03 -04:00
Gabe Black
0c574f1069 missing else
--HG--
extra : convert_revision : 8fe0e00dc3ae70b4449a78c15dd249939e644f02
2006-10-08 18:45:21 -04:00
Gabe Black
a82f017591 bus changes
src/mem/bus.cc:
src/mem/bus.hh:
    minor fix and some formatting changes
src/python/m5/objects/Bus.py:
    changed bits to bytes

--HG--
extra : convert_revision : dcd22205604b7a2727eaf2094084c4858f3589c5
2006-10-08 18:44:49 -04:00
Steve Reinhardt
5df93cc1cd Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().
--HG--
extra : convert_revision : f22ce3221d270ecf8631d3dcaed05753accd5461
2006-10-08 14:48:24 -07:00
Steve Reinhardt
911381321b Update ref stats: ll/sc, cpu_id, new kernel (?)
--HG--
extra : convert_revision : 060cb7319c4474429917a6347a9a47f390208ec8
2006-10-08 17:07:23 -04:00
Gabe Black
63023ba4c2 Merge zizzer.eecs.umich.edu:/bk/newmem
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus

--HG--
extra : convert_revision : 1749397443ccb320d32f8dd23c71ed0431d30cb7
2006-10-08 14:09:13 -04:00
Gabe Black
00481d1f19 A possible implementation of a multiplexed bus.
--HG--
extra : convert_revision : 3c560eda12ffd8ca539c91024baf2770b963ede8
2006-10-08 14:08:58 -04:00
Gabe Black
34b697cd04 Add in HasData, and move the define of NUM_MEM_CMDS to a more visible location.
--HG--
extra : convert_revision : 4379efe892ca0a39363ee04009e1bbb8c8f77afa
2006-10-08 14:04:49 -04:00
Steve Reinhardt
d3fba5aa30 Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory.  *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.

src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
    Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
    and PhysicalMemory.  *No* support for caches or O3CPU.

--HG--
extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
2006-10-08 10:53:24 -07:00
Steve Reinhardt
be36c808f7 Rename some vars for clarity.
--HG--
extra : convert_revision : 765283ae54d2d6b5885ea44c6c1813d4bcf18488
2006-10-08 10:43:31 -07:00
Steve Reinhardt
c2f954ac69 Allocate new thread stacks and shared mem region via Process page table
for Tru64 thread library emulation.

--HG--
extra : convert_revision : dbd307536e260e24ef79130d2aa88d84e33f03d4
2006-10-08 04:29:40 -04:00
Ali Saidi
abc27ae691 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : acab791328d16daace6dfbdc667067ddc68fb6ca
2006-10-07 14:49:10 -04:00
Ron Dreslinski
413a5379b8 Update stats for change in functional path in cache
--HG--
extra : convert_revision : 5abc964ca95b80522266c5c1bc5e661d41f2798a
2006-10-07 12:58:37 -04:00
Ron Dreslinski
467c17fbd9 Fix a missing pointer
--HG--
extra : convert_revision : 2056b530d48fd004ab700f09e58f44adae3ea0e9
2006-10-07 12:55:37 -04:00