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Author SHA1 Message Date
Gabe Black
a46e19f738 A more complete attempt to fix the clock skew. 
--HG--
extra : convert_revision : b2d505de51fc5fcae5177b2a13140729474e249e
 2006-10-27 07:09:14 -04:00
Gabe Black
d5974eff73 Potential fix to clock skew problem. 
--HG--
extra : convert_revision : 51572523190a886fd0ff64817edc88e260c5fa9d
 2006-10-27 06:51:28 -04:00
Gabe Black
f985b752d3 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : ec35a9276ae21e0b9fe820bd700c020e4440a350
 2006-10-27 02:34:26 -04:00
Gabe Black
ca34c62bf9 Update stats for fill/spill handlers 
--HG--
extra : convert_revision : 2ed2e868ccbb3316f84ea691497d2e0dd4ec2416
 2006-10-27 02:21:09 -04:00
Gabe Black
709d50cd6b Got rid of some outdated comments. 
--HG--
extra : convert_revision : 30fa768c4a934cf5f9dc0ad84e0e421327ccbed3
 2006-10-27 01:43:51 -04:00
Gabe Black
b1cc98ed54 Made the regfile compatible with the new definitions in MiscRegFile 
--HG--
extra : convert_revision : d63ea6fb1e549e737204ee6653c06f89ec5e43ef
 2006-10-27 01:43:26 -04:00
Gabe Black
944bfde6b3 Clean up MiscRegFile 
--HG--
extra : convert_revision : 3bc792596c99df3a5c2c82da58b801a63ccf6ddb
 2006-10-27 01:36:42 -04:00
Gabe Black
2cb190d1e3 Reorganized the MiscRegFile 
--HG--
extra : convert_revision : 088112c9b8a4ea09c8015da5a0b65ed2fc9398d2
 2006-10-26 22:48:02 -04:00
Gabe Black
f33bab2386 Cleaned up the decoder slightly. 
--HG--
extra : convert_revision : a7050aa8768c132f0161f00ba17ae02d71f0b829
 2006-10-26 22:47:17 -04:00
Gabe Black
f88b90dd56 Added a few functions to stuff values into bitfields in an instruction. 
--HG--
extra : convert_revision : 507d7e13fd6276acf36b75eba31dff5e8080113f
 2006-10-26 20:25:22 -04:00
Gabe Black
d1b30102fd Changed the number of register windows to be more realistic. 
--HG--
extra : convert_revision : ae557307f377b19bae82226dafa8b4b2654cae52
 2006-10-26 20:24:01 -04:00
Gabe Black
5024b20278 Got rid of some debug output 
--HG--
extra : convert_revision : 6e98cf839dc92bde5f06f9b9bf11ca6ac661c907
 2006-10-26 20:23:00 -04:00
Gabe Black
e441be1b82 Change the default function from setMiscRegWithEffect to setMiscReg 
--HG--
extra : convert_revision : bedf422d51a52b009390b1e94f5330f752be2b87
 2006-10-26 20:22:23 -04:00
Lisa Hsu
2f30c2b4c9 Merge zizzer:/bk/newmem 
into  zed.eecs.umich.edu:/z/hsul/work/m5/clean

--HG--
extra : convert_revision : cb3f718bdcbd52540747a2696fb37bb4fcfe27a3
 2006-10-26 16:04:27 -04:00
Lisa Hsu
260b3c0cf0 se.py: 
make the same os.getcwd fix ali made in fs.py, make connectMemPorts occur after caches are created.

configs/example/se.py:
    make the same os.getcwd fix ali made in fs.py, make connectMemPorts occur after caches are created.

--HG--
extra : convert_revision : 9760ae073d97cd62d3e44f10199d31cce79d4a1d
 2006-10-26 16:04:09 -04:00
Ali Saidi
d626a32c52 Merge zizzer:/bk/newmem 
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 473901bcd44bd2c563a3293d7326cd5aed8b630f
 2006-10-26 15:49:19 -04:00
Ali Saidi
f4be29804f Fix simple timing port keep a list of all packets, have only one event, and scan all packets on a functional access. 
--HG--
extra : convert_revision : c735a6408443b5cc90d1c1841c7aeb61e02ec6ae
 2006-10-25 18:34:21 -04:00
Gabe Black
93b3176d4e Fixed the priv instruction format. 
src/arch/sparc/isa/formats/priv.isa:
    Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated.
src/arch/sparc/isa/operands.isa:
    Added an Hpstate operand, and adjusted the numbering.

--HG--
extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
 2006-10-25 17:58:44 -04:00
Gabe Black
99d9d40e6c Implemented the saved and restored instructions, fixed up register window instructions so that the cwp is modified at the correct time (when handling the fault), and fixed the "done" instruction. 
--HG--
extra : convert_revision : 3c9144422f087af1d375782cce1c9b77ca7936c9
 2006-10-25 17:54:14 -04:00
Gabe Black
047455625e Fixed the bitfield FCN to include the right bits. 
--HG--
extra : convert_revision : 040beb4dd982784773c3c3ad04cc48c2dc98b58c
 2006-10-25 17:50:39 -04:00
Gabe Black
e2eef8859b Implemented the SPARC fill and spill handlers. 
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
    Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
    Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart.

--HG--
extra : convert_revision : 59adb96570cce86f373fbc2c3e4c05abe1742d3b
 2006-10-25 17:49:41 -04:00
Ron Dreslinski
eda7148af2 Fix fixPacket functionality to calculate sizes properly 
src/mem/packet.cc:
    Copy size is calculated by END-BEGIN not BEGIN-END

--HG--
extra : convert_revision : 0e2725c5551f8f70ff05cb285e0822afc0bb3f87
 2006-10-25 14:14:37 -04:00
Gabe Black
1b1495930c Replace the Alpha No op with a SPARC one. 
--HG--
extra : convert_revision : bed03e63dc80bf24f21bad08e6553d7aab92c7b3
 2006-10-24 15:50:41 -04:00
Ali Saidi
86bd01dfc9 Fix fs.py. Lisa did you test this? Is there some wierd python version thing? 
--HG--
extra : convert_revision : 6df5f90d5b66e7af27d4f524744b9dc3c703a588
 2006-10-24 13:10:31 -04:00
Ali Saidi
0f98905ecc Merge zizzer:/bk/newmem 
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 4db140e6e8408b3ed39da327515b8e88a2701e6b
 2006-10-24 12:59:19 -04:00
Ali Saidi
650ebe4ec3 Add more traceflags for ethernet 
--HG--
extra : convert_revision : a5025f501d72626d1bcb4dcc24ee353ceb160ce7
 2006-10-24 12:59:07 -04:00
Steve Reinhardt
06482e6eed Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem 
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : a077304e608753f50f4a12216901d156469eebe4
 2006-10-24 11:50:20 -04:00
Lisa Hsu
3922b2e076 warmup of 1B cpu cycles. 
configs/example/fs.py:
configs/example/se.py:
    warm up of 1B CPU cycles

--HG--
extra : convert_revision : 0f3263f466fde4cd86e0663930e83617a6b3faad
 2006-10-23 19:32:57 -04:00
Lisa Hsu
764f27a0c9 Merge zizzer:/bk/newmem 
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : bb58679e101570d50c040519fb08ffbabfee7416
 2006-10-23 18:46:05 -04:00
Lisa Hsu
4da3938ed9 get rid of the "resume" step at the end of changeToTiming/Atomic because this will cause an assertion when you do the CPU switch. instead, push the responsibility of the resume upwards towards the user - documented in se.py and fs.py so it should be ok. 
--HG--
extra : convert_revision : 7530cf140844e18cc26df80057f8760f29ec952b
 2006-10-23 18:45:30 -04:00
Lisa Hsu
0a2387f38c make this parallel to the other cpu types so that resume works correctly. 
--HG--
extra : convert_revision : 3c165af27ea0e6c7f2a17819c1717d8900f54cc1
 2006-10-23 18:43:56 -04:00
Lisa Hsu
049f8d53a9 make a lot of the same changes as to fs.py for checkpointing. 
1) rearrange the options to be in a nice logical order
2) add an option for what i call "standard switch", which is from simple->timing->detailed
3) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
4) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first

--HG--
extra : convert_revision : 8d905e1b297ae664d60f8c8ba48b2aac25437fc6
 2006-10-23 18:42:46 -04:00
Lisa Hsu
40a04f2f40 changes regarding fs.py 
1) rearrange the options to be in a nice logical order
2) add an option for what i call "standard switch", which is from simple->timing->detailed
3) change the client/server naming system to testsys/drivesys
4) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
5) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first

doesn't fully work because of a caching issue, but the python side of things i think should work - the counterpart of se.py does work.
i think i should factor out a lot of the common code in both, but i'll do that after this checkin, just to get this in the tree.

configs/example/fs.py:
    1) rearrange the options to be in a nice logical order
    2) add an option for what i call "standard switch", which is from simple->timing->detailed
    3) change the client/server naming system to testsys/drivesys
    4) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
    5) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first

--HG--
extra : convert_revision : 078e22800ff83f6e950bf5cc6fb16a98320e7c51
 2006-10-23 18:07:51 -04:00
Gabe Black
ef8b7713ca Minor compile fix. Not sure why this is broken. 
--HG--
extra : convert_revision : 6f181b15f37114ca0a3965cabcb2036bd2f97916
 2006-10-23 11:17:59 -04:00
Gabe Black
18b2d94b8c Move around more SPARC memory code, and make block memory operations work with the timing cpu 
--HG--
extra : convert_revision : 37358504c4d05d78d08c19ba3d0c99d38c4babf5
 2006-10-23 11:17:15 -04:00
Gabe Black
466c387318 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  zeep.eecs.umich.edu:/home/gblack/m5/newmem

--HG--
extra : convert_revision : cb15101d24ef2969e1819d6bdeeb2dd1f23f02d1
 2006-10-23 09:44:58 -04:00
Gabe Black
274d2670a1 Add reference outputs for SPARC on the atomic timing cpu model 
--HG--
extra : convert_revision : b64ff7c05504da6112631baaae8f0d927469e16f
 2006-10-23 07:57:16 -04:00
Gabe Black
20208d00e6 Broke Load/Store instructions into microcode, and partially refactored memory operations in the SPARC ISA description. 
--HG--
rename : src/arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats/formats.isa
rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/basicmem.isa
rename : src/arch/sparc/isa/formats/blockmem.isa => src/arch/sparc/isa/formats/mem/blockmem.isa
rename : src/arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem/mem.isa
extra : convert_revision : dbbb00f997a102871b084b209b9fa08c5e1853ee
 2006-10-23 07:55:52 -04:00
Gabe Black
e9908e3c85 Don't let interupts interupt microcode at undesired points. 
--HG--
extra : convert_revision : a8ddc6b213b1a1b0d9c5cd194b88ac0c6bfb2a21
 2006-10-23 02:39:02 -04:00
Gabe Black
a8973c6054 Files in base shouldn't depend on things in sim. Changed "sim/host.hh" to <inttypes.hh> 
--HG--
extra : convert_revision : c1e46c012a26cdb0603416f8e8a99e0ecb1c09bc
 2006-10-23 02:37:54 -04:00
Gabe Black
f31d73a433 Start making memory ops work with InitiateAcc and CompleteAcc, and some minor cleanups 
--HG--
extra : convert_revision : 178a8c5d0506c75ad7a7e8d691c8863235ed7e95
 2006-10-23 02:36:46 -04:00
Gabe Black
3d6ff82552 Change the default constructors to take ExtMachInsts rather than regular MachInsts 
--HG--
extra : convert_revision : 8fa34f82e0cbf5ce81775d572b182826c578581f
 2006-10-23 02:32:58 -04:00
Steve Reinhardt
e321a21e27 Clean up cache DPRINTFs 
--HG--
extra : convert_revision : f836e77efd40e25259d7794dd148696586b79a09
 2006-10-22 21:07:38 -07:00
Steve Reinhardt
1b21d9ba5e s/pktuest/request/ (all in comments) 
--HG--
extra : convert_revision : 7ce779242a15245a20322c0b6c40d02c8ddd15ad
 2006-10-22 20:38:34 -07:00
Steve Reinhardt
199084b339 Add DPRINTF for non-timed quiesce. 
--HG--
extra : convert_revision : 5487f4fc07dbea6e5a651c104ea1d2fe864fb057
 2006-10-22 16:22:45 -07:00
Steve Reinhardt
d2856c2fde Add mutex test to Benchmarks.py. 
--HG--
extra : convert_revision : 9b4f1ce9a181ac5a01e5b6a68067079969dfe9ce
 2006-10-22 12:52:58 -04:00
Steve Reinhardt
968311d096 Another missing case in a switch (like Nate's earlier fix). 
--HG--
extra : convert_revision : b2f195c29861a09e9dd99aefcf4a173be2f8c97c
 2006-10-22 12:51:49 -04:00
Steve Reinhardt
810dee6e98 Have tracediff print warning if no traceflags are set. 
Elaborate on description a bit.

--HG--
extra : convert_revision : 2649961b53d6fb2774ddfb60219415ae4251db2d
 2006-10-22 12:51:00 -04:00
Steve Reinhardt
5e2263fc52 Small bug fixes for timing LL/SC. Better now but 
not necessarily 100% there yet.

src/mem/cache/cache_impl.hh:
    Generate response packet on failed store conditional.
src/mem/packet.hh:
    Clear packet flags when reinitializing.
    (SATISFIED in particular is one we don't want to leave set.)

--HG--
extra : convert_revision : 29207c8a09afcbce43f41c480ad0c1b21d47454f
 2006-10-21 23:35:00 -07:00
Steve Reinhardt
0159529343 Add Quiesce trace flag to track CPU quiesce/wakeup events. 
--HG--
extra : convert_revision : 23be99d0fe6e2184523efe5d9e0a1ac7bf19d087
 2006-10-21 23:32:14 -07:00