Commit graph

239 commits

Author SHA1 Message Date
Kevin Lim
70b35bab57 Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs.
They are now accessed by calling readMiscReg()/setMiscReg() on the XC.  Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future).

arch/alpha/alpha_memory.cc:
    Change accesses to IPR to go through the XC.
arch/alpha/ev5.cc:
    Change accesses for IPRs to go through the misc regs.
arch/alpha/isa/decoder.isa:
    Change accesses to IPRs to go through the misc regs.  readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect().
arch/alpha/isa/fp.isa:
    Change accesses to IPRs and Fpcr to go through the misc regs.
arch/alpha/isa/main.isa:
    Add support for all misc regs being accessed through readMiscReg() and setMiscReg().  Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index.
arch/alpha/isa_traits.hh:
    Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs.
    Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect.  The latter are basically the original read/write IPR functions, while the former are normal reads/writes.

    The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs.
arch/alpha/stacktrace.cc:
cpu/simple/cpu.cc:
dev/sinic.cc:
    Change accesses to the IPRs to go through the XC.
arch/alpha/vtophys.cc:
    Change access to the IPR to go through the XC.
arch/isa_parser.py:
    Change generation of code for control registers to use the readMiscReg and setMiscReg functions.
base/remote_gdb.cc:
    Change accesses to the IPR to go through the XC.
cpu/exec_context.hh:
    Use the miscRegs to access the lock addr, lock flag, and other misc registers.
cpu/o3/alpha_cpu.hh:
cpu/simple/cpu.hh:
    Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions.
cpu/o3/alpha_cpu_impl.hh:
    Change accesses to the IPRs to go through the miscRegs.
    For now comment out some of the accesses to the misc regs until the proxy exec context is completed.
cpu/o3/alpha_dyn_inst.hh:
    Change accesses to misc regs to use readMiscReg and setMiscReg.
cpu/o3/alpha_dyn_inst_impl.hh:
    Remove old misc reg accessors.
cpu/o3/cpu.cc:
    Comment out old misc reg accesses until the proxy exec context is completed.
cpu/o3/cpu.hh:
    Change accesses to the misc regs.
cpu/o3/regfile.hh:
    Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg.  They are dummy functions for now until the proxy exec context is completed.
kern/kernel_stats.cc:
kern/system_events.cc:
    Have accesses to the IPRs go through the XC.
kern/tru64/tru64.hh:
    Have accesses to the misc regs use the new access methods.

--HG--
extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
2006-02-27 11:44:35 -05:00
Ali Saidi
4f831bc561 ev5.cc:
SCCS merged

arch/alpha/ev5.cc:
    SCCS merged

--HG--
extra : convert_revision : 9d70c1d461dab0ec016fd0616d74a49942aac659
2006-02-23 15:08:08 -05:00
Ali Saidi
e1c3acd91c Merge zizzer:/bk/m5
into  zeep.eecs.umich.edu:/z/saidi/work/m5.head

cpu/simple/cpu.cc:
    remove initCPU from constructor
dev/alpha_console.cc:
    we are panicing, so no need to return a fault

--HG--
extra : convert_revision : 72389ea0c96e91a55f35b884200325224bfb6ed9
2006-02-23 15:06:06 -05:00
Ali Saidi
1166d4f0bf Get rid of the xc from the alphaAccess/alphaConsole backdoor device.
Now allocate an array of stacks indexed by cpu number which specify
cpu stacks and are initialized by cpu 0. Othe cpus spin waiting for
their stacks before continuing. This change *REQUIRES* a the new
console code to operate correctly.

arch/alpha/ev5.cc:
    Add cpuId to initCPU/initIPR functions
cpu/o3/cpu.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Move the cpu initilization into an init() function since it now needs
    the CPU id which isn't known at construction
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
    instead of the bootstrap variables, add space for 64 cpu stacks in the
    alpha access structure.
sim/system.cc:
    start all cpus immediately rather than just the first one

--HG--
extra : convert_revision : 28c218af49d885a0f203ada419f16f25d5a3f37b
2006-02-23 14:50:16 -05:00
Steve Reinhardt
99484cfae8 Create a Builder object for .isa files in arch/SConscript.
Start using SCons File objects to avoid fixed paths in
subordinate SConscripts.

SConscript:
    Push isa_parser stuff (including .isa scanner) down into
    arch/SConscript.
arch/SConscript:
    Create a Builder object for .isa files, including existing scanner.
    Return file objects generated by isa-specific SConscript
    back up to parent.
arch/alpha/SConscript:
arch/mips/SConscript:
arch/sparc/SConscript:
    Convert sources to scons File objects, so file names can be specified
    relative to the current directory.
    Invoke new builder for isa description, and get generated sources from
    there (instead of listing them explicitly).
arch/isa_parser.py:
    Get rid of third argument ("include_path").
    It was a pain to generate this from scons, and it turned out
    it's not needed anyway, since the only included file
    (decoder.hh) will be in the same directory as the sources.

--HG--
extra : convert_revision : 36861bcef36763f229704d8cb7a642b4486a3581
2006-02-23 14:31:15 -05:00
Steve Reinhardt
c13ea339dc Add pipe() syscall to Alpha Linux emulation.
arch/alpha/alpha_linux_process.cc:
    Add pipeFunc.

--HG--
extra : convert_revision : c094d2dff993d5e60bc43b7cd4b9586c15c634a3
2006-02-23 08:16:59 -05:00
Steve Reinhardt
9a4c0f12ef Clean excess comments out of SConscripts.
SConscript:
arch/alpha/SConscript:
    Clean out excess comments.

--HG--
extra : convert_revision : 7aae68d36f9fce5f236d117d803b5e3cd4a3769d
2006-02-22 21:11:45 -05:00
Gabe Black
8d80fd1477 Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed.
--HG--
extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb
2006-02-21 20:10:40 -05:00
Gabe Black
3f7979c99d Made Addr a global type
--HG--
extra : convert_revision : 869bd9fa5d8591115ac9b4a7401eb2490986b835
2006-02-21 03:38:21 -05:00
Gabe Black
7c642b7106 Reapplied changes which were undone by a pull
arch/alpha/faults.hh:
kern/linux/linux.hh:
    Added typedef for Addr
kern/tru64/tru64.hh:
    Fixed up namespaces

--HG--
extra : convert_revision : bf968e615bc0acc96abeb0eec0872f5b02b5a065
2006-02-19 04:00:05 -05:00
Gabe Black
f721a4d9ad Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

arch/alpha/faults.hh:
    ur
    Using cleaned up fault class deiffinitions

--HG--
extra : convert_revision : a600950d539be2be73358f072aa5426456bf3d2d
2006-02-19 03:20:05 -05:00
Gabe Black
463aa6d49d Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.
arch/alpha/alpha_linux_process.cc:
    Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
    Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
    Added using directive for AlphaISA
arch/alpha/ev5.hh:
    Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
    Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
    Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
    Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
    Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
    Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
    Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
    Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
    Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
    Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
    Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
    Added a typedef for Addr
base/loader/symtab.hh:
    Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
    Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
    Added typedefs for Addr and MachInst
cpu/base.cc:
    Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
    Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
    Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
    Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
    Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
    Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
    Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
    Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
    Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
    Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
    Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
    untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
    Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
    Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
    Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
    Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
    Cleaned up namespace issues
cpu/o3/cpu.hh:
    Cleaned up namespace usage
cpu/o3/decode.hh:
    Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
    Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
    Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
    Removed typedef of ISA
cpu/o3/iew_impl.hh:
    Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
    Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
    Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
    Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
    Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
    Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
    Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
    Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
    Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
    Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
    Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
    Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
    Untemplatized StaticInst
cpu/static_inst.hh:
    Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
    Added using namespace AlphaISA
dev/simple_disk.hh:
    Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
    Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
    Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
    Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
    Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
    Added TheISA to Addr type in structs
sim/process.hh:
    Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
    Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
    Added typecast for Addr, and TheISA namespace specifier for where needed

--HG--
extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
2006-02-19 02:34:37 -05:00
Ali Saidi
14f2cdb1a1 Merge zizzer:/bk/m5
into  pb15.local:/Users/ali/work/m5.head

--HG--
extra : convert_revision : 774e4afbb0f9c3ae62843138b6d7195ea184ff92
2006-02-19 00:47:45 -05:00
Ali Saidi
00d58aeb4d forgot a negative sign
--HG--
extra : convert_revision : 9cdb00198979fca831d3e6840f9c534671ccead3
2006-02-19 00:28:53 -05:00
Ali Saidi
53d2c9398e Move Linux/Tru64 architecture independent code into kern/*
leaving dependent code making way  for solaris linux syscall emu.

SConscript:
    Add two new files for syscall emulation
    Add getDesc() function
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    move architecture independent code into kern/linux/linux.(hh|cc)
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.hh:
    Add getDesc function
kern/linux/linux.hh:
    move generi linux syscall emulation code into kern/linux
kern/tru64/tru64.hh:
    move generi tru64 syscall emulation code into kern/tru64
sim/process.cc:
sim/process.hh:
    Push the function determination and calling stuff down to LiveProcess
    and out of the Linux/Tru64 classes respectively
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    fnctl implementation was identical in tru64 and linux so moved to generic

--HG--
extra : convert_revision : 103293dbe6fe2f7892de4929d17dc085def77026
2006-02-18 23:44:22 -05:00
Kevin Lim
d6a330ebb9 Remove fake fault.
Switch fault pointers to const pointers to prevent them from accidentally being changed.
Fix some coding style.

arch/alpha/ev5.cc:
cpu/o3/commit_impl.hh:
kern/kernel_stats.hh:
    Remove fake fault.
arch/alpha/faults.cc:
    Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally.
arch/alpha/faults.hh:
    Fix to have normal m5 line length limit, change pointers to const pointers.
sim/faults.cc:
sim/faults.hh:
    Remove fake fault, change pointers to const pointers.

--HG--
extra : convert_revision : 01d4600e0d4bdc1d177b32edebc78f86a1bbfe2e
2006-02-16 14:55:15 -05:00
Kevin Lim
c7624c26e7 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-new

arch/alpha/isa/mem.isa:
    Hand merge.

--HG--
extra : convert_revision : c557aa4c867d84ab01139e509ee9f2ed05dd8ea0
2006-02-16 12:03:44 -05:00
Kevin Lim
485568efa9 Fixes to handle generating the initiateAcc and completeAcc functions a little more cleanly.
arch/alpha/isa/mem.isa:
    Avoid explicitly declaring the Mem variable.  Instead break up the code blocks used to generate the initiate and complete functions.  The templates reflect which operands need to be declared for each function (src, dest, or both).

    Loads use both the EA code and mem acc code for the initiate, and memacc code and postacc code for the complete.
    Stores use both the EA code and mem acc code for the initiate, and only post acc code for the complete.
arch/isa_parser.py:
    Remove hack for mem ops.

--HG--
extra : convert_revision : a367797a2cb698762bfc27be1da00bcbe9367150
2006-02-16 11:55:28 -05:00
Gabe Black
00f451cc02 Some changes which weren't needed before doing a bk pull were needed afterwards, for some reason.
arch/alpha/ev5.cc:
    Took out the unnecessary check for a null Fault pointer.
arch/alpha/isa/mem.isa:
    Changed Fault to Fault *, and removed underscores from fault names.

--HG--
extra : convert_revision : 367a58a375f911185ddcc5fc826034af96427461
2006-02-16 02:08:13 -05:00
Gabe Black
b161d2a731 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : d8626acb2686e123ad0bb6cf94e85c992657470d
2006-02-16 01:25:48 -05:00
Gabe Black
10c79efe55 Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA.
SConscript:
    The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
    Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
    Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
    Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
    Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
    Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
    Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
    Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
    Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
    Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
    Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
    Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
    Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
    Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
    Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
    Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
    Changed Fault to Fault *
dev/ns_gige.cc:
    Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
    Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
    Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
    Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
    Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
    This allocates the system wide faults.
sim/faults.hh:
    This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Removed the underscores from fault names.

--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
2006-02-16 01:22:51 -05:00
Kevin Lim
2d04f18674 Gives separate methods for initiating and completing a memory access, which will be helpful for the merged memory model.
arch/alpha/isa/mem.isa:
    Include methods that allow a memory operation to be split between the part that initiates the access, and the part that completes the access.  In these functions the Mem variable is explicitly declared; in the default execute functions, the Mem variable is still handled through %(op_decl)s.
arch/isa_parser.py:
    Include recording the type of the memory access variable so that it can be used if it needs to be explicitly declared in a template.

    Have memory operands consider themselves neither a source nor a destination to avoid including themselves on the op_src_decl list or the op_dest_decl list.

    Record op_src_decl and op_dest_decl lists to allow for declaring only source or destination operands.  This is needed for the split memory access methods.

--HG--
extra : convert_revision : f674f7a2f747ae40ba8c3a0933b0337c87ee0b6c
2006-02-15 13:05:21 -05:00
Ali Saidi
7b42d61f13 Merge zizzer:/bk/m5
into  pb15.local:/Users/ali/work/m5.head

sim/byteswap.hh:
    SCCS merged

--HG--
extra : convert_revision : 65989fef265ddfafb59a6c96e3cdde76eb3e071d
2006-02-15 01:27:06 -05:00
Ali Saidi
18a0fa3e0c endian fixes and compiles on mac os x
arch/alpha/alpha_linux_process.cc:
    add endian conversions for fstat functions
arch/alpha/alpha_tru64_process.cc:
    add endian conversions for various functions
sim/byteswap.hh:
    for some reason gcc on macos really wants long and unsigned long
    Why int32_t and uint32_t isn't sufficient I don't know.
sim/process.cc:
sim/syscall_emul.hh:
    endian fixes

--HG--
extra : convert_revision : ce625d5660b70867c43c74fbed856149c0d8cd36
2006-02-15 01:23:13 -05:00
Gabe Black
085b73fe44 Fixed a path in the alpha isa description.
--HG--
extra : convert_revision : 2a73ef7703ffe5c5232619698a16c8b4ee265a21
2006-02-14 03:57:42 -05:00
Gabe Black
19e5efed03 Pseudo instructions are now passed whatever instructions they need by the decoder, rather than extracting them explicitly. This lets most of the pseudo instruction code to be shared across architectures.
SConscript:
    Moved pseudo_inst.hh from targetarch to full system sources
arch/alpha/SConscript:
    Moved pseudo_inst.cc out of the alpha specific sources
arch/alpha/isa/decoder.isa:
    The decoder now pulls out the arguments for the pseudo instructions based on the alpha ABI
arch/alpha/isa/main.isa:
    Registers 16, 17 and 18 are used to get parameters for the pseudo instructions and can be referred to explicitly
sim/pseudo_inst.cc:
    Changed some include paths to reflect that pseudo_inst.hh is now outside of the alpha directory. Also, instead of extracting their parameters directly, they're passed in as regular function arguments.
sim/pseudo_inst.hh:
    Changed the function prototypes to include the functions parameters, now that they aren't extracted from the execution context.

--HG--
rename : arch/alpha/pseudo_inst.cc => sim/pseudo_inst.cc
rename : arch/alpha/pseudo_inst.hh => sim/pseudo_inst.hh
extra : convert_revision : 76ce768cf1d8a838aa7b64878a7ab4c4215ac999
2006-02-12 17:38:10 -05:00
Gabe Black
2c5e03550a Removed isa_traits.hh from targetarch, moved vptr.hh from arch/alpha to sim, fixed an include to have the new location, and removed an ambiguating function declaration in byteswap.hh.
SConscript:
    Moved isa_fullsys_traits.hh out of targetarch, since the only place it's included, and the only place the comments in the file say it should be included, is in the alpha isa_traits.hh
    targetarch/isa_traits.hh is now included through arch/isa_traits.hh
    vptr.hh was removed from targetarch, and moved to sim
arch/alpha/pseudo_inst.cc:
    Moved vptr.hh from targetarch to sim
base/loader/object_file.hh:
base/loader/symtab.hh:
cpu/base.hh:
dev/ide_disk.cc:
    Changed the include of isa_traits.hh from targetarch to arch
cpu/static_inst.hh:
dev/platform.hh:
dev/simple_disk.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/mbuf.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/process.hh:
sim/syscall_emul.hh:
    Changed the include of isa_traits.hh from targetarch to arch.
kern/linux/linux_threadinfo.hh:
    Changed the include of vptr.hh from targetarch to sim.
sim/byteswap.hh:
    Removed the line declaring swap_byte(long), since it ambiguates with swap_byte(int32_t)
sim/vptr.hh:
    Fixed the assert in the equals operator.
    Changed the AlphaISA namespace reference to TheISA.
    Changed arch/alpha/vtophys.hh to targetarch/vtophys.hh, since this file is now for all architectures.
    Added an include of arch/isa_traits.hh so that TheISA would be defined.

--HG--
extra : convert_revision : e3c6ac17ed0277cfeba1d35cd63eba66eba5996f
2006-02-12 12:40:58 -05:00
Gabe Black
4d4c105ac5 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : baf9b0eb84df7da8152ddf9a25264e041a24b8ca
2006-02-12 12:17:51 -05:00
Gabe Black
47a065d9f0 vptr.hh:
Rename: arch/alpha/vptr.hh -> sim/vptr.hh

--HG--
rename : arch/alpha/vptr.hh => sim/vptr.hh
extra : convert_revision : 345745efec49f6169d1d9f61fd590240a995373b
2006-02-12 12:14:14 -05:00
Steve Reinhardt
79613686f0 Polishing of isa_parser.py internal operand handling, resulting in
minor change to syntax of 'def operands' in ISA descriptions.

arch/alpha/isa/main.isa:
arch/mips/isa/operands.isa:
arch/sparc/isa/operands.isa:
    Change 'def operands' statement to work with new
    isa_parser changes.
arch/isa_parser.py:
    Merge OperandTraits and OperandDescriptor objects into a
    unified hierarchy of Operand objects.
    Required a change in the syntax of the 'def operands'
    statement in the ISA description.

--HG--
extra : convert_revision : cb43f1607311497ead88ba13953d410ab5bc6a37
2006-02-12 00:31:19 -05:00
Steve Reinhardt
3cc6c59582 Add keyword parameters and list-valued arguments to
instruction format functions in ISA description language.

Take advantage of these features to clean up memory
instruction definitions in Alpha.

arch/alpha/isa/decoder.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
    Take advantage of new keyword parameters to disambiguate
    instruction vs. memory-request flags, and to provide
    a default EA calculation for memory ops (since 99% of them
    are the same).
arch/isa_parser.py:
    Add two new features to instruction format functions:
    - Keyword parameters, a la Python.
    - List-valued arguments.

    Also export makeList() function to Python code blocks,
    as this is handy for dealing with flags.

--HG--
extra : convert_revision : 99bbbaa2e765230aa96b6a06ed193793325f9fb0
2006-02-11 15:11:00 -05:00
Ali Saidi
59ba3d463c fix #if. I wonder why my compiler had no issues. Even though it is clearly
wrong

arch/alpha/alpha_linux_process.cc:
    fix #if. I wonder why my compiler had no issues

--HG--
extra : convert_revision : 880a0442b28811db5ec548ce940060d4b26ec634
2006-02-11 11:01:51 -05:00
Ali Saidi
96d6ac441c hello world works on a BE host for a LE guest
arch/alpha/alpha_linux_process.cc:
    Add endian conversions to fstat
sim/byteswap.hh:
    for some reason I don't understand g++ really wanted a long version defined
    even though int32_t should be the same.

--HG--
extra : convert_revision : 5bfe9d3f0b31824fa5a7ae3f51fd0be5ed4d555d
2006-02-11 00:55:36 -05:00
Ali Saidi
f2e97427be Merge zizzer:/bk/m5
into  pb15.local:/Users/ali/work/m5.head

--HG--
extra : convert_revision : b8631bcea38e3a75e4442927500ddfc7763ba9cf
2006-02-10 20:06:44 -05:00
Ali Saidi
fb7899aa68 fix problems on darwin/*BSD for syscall emulation mode
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    fixup for bsd hosts. Some headers are included by default which means that
    more variables need TGT_ prefixes and there isn't a stat call (everything
    is a stat64 call) so we have to work around that a bit
base/intmath.hh:
base/socket.cc:
    this is no longer needed with mac os 10.4
cpu/inst_seq.hh:
    just use a uint64_t instead of long long
cpu/o3/inst_queue_impl.hh:
    I much cleaner way to get max int
sim/syscall_emul.hh:
    fix stat64 problems on *BSD

--HG--
extra : convert_revision : 9eef5f896e083ae1774e818a9765dd83e0305942
2006-02-10 14:21:32 -05:00
Steve Reinhardt
3923eec0ef Change how memory operands are handled in ISA descriptions.
Should enable implementation of split-phase timing loads
with new memory model.
May create slight timing differences under FullCPU, as I
believe we were not handling software prefetches correctly
before when the split MemAcc/Exec model was used.  I haven't
looked into this in any detail though.

arch/alpha/isa/decoder.isa:
    HwLoadStore format split into separate HwLoad and
    HwStore formats.
    Copy instructions now fall under MiscPrefetch format.
    Mem_write_result is now just write_result in store
    conditionals.
arch/alpha/isa/mem.isa:
    Split MemAccExecute and LoadStoreExecute templates
    into separate templates for loads and stores; now
    that memory operands are handled differently from
    registers, it's impossible to have a single template
    serve both.
    Also unified the handling of "regular" prefetches
    (loads to r31) and "misc" prefetches (e.g., wh64)
    under the new scheme.  It looks like SW prefetches
    were not handled correctly in FullCPU up til now,
    since we generated an execute() method for the outer
    instruction but didn't generate a proper method for
    MemAcc::execute() (instead getting a default no-op
    method for that).
arch/alpha/isa/pal.isa:
    Split HwLoadStore into separate HwLoad and HwStore
    formats to select proper template (see change to
    mem.isa in this changeset).
arch/isa_parser.py:
    Stop trying to treat memory operands like register
    operands, since we never used them in a uniform way
    anyway, and it made it impossible to do split-phase
    loads as needed for the new CPU model.  Now there's no
    more 'op_mem_rd', 'op_nonmem_rd', etc.: 'op_rd' just does
    register operands, and the template code is responsible
    for formulating the call to the memory system.  Right now
    the only thing exported by InstObjParams is a new attribute
    'mem_acc_size' which gives the memory access size in bits,
    though more attributes can be added if needed.

    Also moved code in findOperands() method to
    OperandDescriptorList.__init__(), which is where it belongs.

--HG--
extra : convert_revision : 6d53d07e0c5e828455834ded4395fa40f9146a34
2006-02-10 09:12:55 -05:00
Steve Reinhardt
dd473ecd57 Split Alpha ISA description into multiple files
(thanks to Gabe's include feature!).

arch/alpha/isa/main.isa:
    Split out into multiple .isa files.

--HG--
extra : convert_revision : 30d8edf74ea194d4a208febf1e66edc72a7dbd5d
2006-02-09 23:02:38 -05:00
Gabe Black
f444a7e799 Moved the alpha isa_desc to conform to the new naming system.
--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
extra : convert_revision : a3cc14c202ae606db270c2c29847170d90c05216
2006-02-08 02:17:47 -05:00
Gabe Black
e59fdcdd39 Some fixups
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    Replaced the namespace declaration with including arch/alpha/isa_traits.hh

--HG--
extra : convert_revision : 07cb73a9f30f0e165809668f9baff6a3e3f94580
2006-02-08 01:57:47 -05:00
Gabe Black
82f2ae56ed Alot of changes to push towards ISA independence. Highlights are renaming of the isa_desc files, movement of byte_swap.hh into sim, and the creation of arch/isa_traits.hh
SConscript:
    Moved some files out of targetarch. The either no longer need to be there, never needed to be there, or should be referred to directly in arch/alpha due to there strictly alpha content.
arch/alpha/isa_traits.hh:
    Added alpha's endianness to it's isa_traits.hh
arch/mips/isa_traits.hh:
    Added MIPS endianness to it's isa_traits.hh
arch/sparc/isa_traits.hh:
    Added SPARCs endianess to it's isa_traits.hh
build/SConstruct:
    Added MIPS as a valid architecture
cpu/exec_context.hh:
    Included arch/isa_traits.hh to bring in the endianness of the system.
cpu/o3/alpha_cpu.hh:
    Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding of little endianness
cpu/o3/fetch_impl.hh:
kern/freebsd/freebsd_system.cc:
    Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endianness.
sim/system.cc:
    Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endian.

--HG--
extra : convert_revision : b1ab34b7569db531cd1c74f273b24222e63f9007
2006-02-08 01:03:55 -05:00
Gabe Black
2939a7089a byte_swap.hh was removed from arch/alpha/, and replaced by sim/byteswap.hh. The new file uses LittleEndianGuest and BigEndianGuest namespaces to allow selecting the appropriate functions.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    Added the endianness namespace. This may change.
cpu/exec_context.hh:
    Changed the include path for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/o3/alpha_cpu.hh:
    Forced LittleEndianness, for lack of a better solution.
cpu/o3/alpha_cpu_impl.hh:
    Cleared away some commented out code.
cpu/o3/fetch_impl.hh:
    Changed the include patch for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/simple/cpu.cc:
    Added an include for byteswap.hh, and fixed the SimpleCPU to LittleEndian. This cpu only does alpha, so that's fine.
dev/disk_image.cc:
    Changed the include path of byteswap.hh
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
    Added an include for byteswap.hh, and forced LittleEndianness for lack of a better solution.
sim/system.cc:
    Forced LittleEndianness for lack of a better solution.

--HG--
extra : convert_revision : b95d3e1265a825e04bd77622a3ac09fbac6bd206
2006-02-03 00:16:44 -05:00
Gabe Black
89596f0cfa Some stuff aparently didn't get committed which was from before the new repository was created.
SConscript:
    There is a new SConscript in the arch/alpha directory which has the alpha specific files. To add files for an arch, a similar file should be created.
arch/isa_parser.py:
    The isa parser now supports include directives. These are done with ##include
build/SConstruct:
    The target directory is passed on so that the architecture specific SConscript can have it. Also, sparc was added as a valid architecture type.
arch/alpha/SConscript:
    This SConscript adds the alpha specific source
arch/sparc/isa_desc/operands.h:
    This sets up the operand types that the sparc isa uses
arch/sparc/isa_traits.cc:
    Implementation of sparc specific things, like a register file with windows
build/build_options/default/SPARC_SE:
    The default options for a sparc syscall emulation build.

--HG--
extra : convert_revision : 1afedae61dc8cae0d59d3bf1d41420d929be2efd
2006-01-24 19:57:17 -05:00
Steve Reinhardt
0cdcb08d90 Change base/intmath.{cc,hh} to follow m5 style.
arch/alpha/alpha_tru64_process.cc:
base/intmath.hh:
base/statistics.cc:
base/str.cc:
cpu/o3/btb.cc:
sim/process.cc:
sim/syscall_emul.hh:
    Rename intmath.hh functions to follow m5 style
    (RoundUp -> roundUp, etc.).
base/intmath.cc:
    Rename intmath.hh functions to follow m5 style
    (RoundUp -> roundUp, etc.).
    Also reindent code in m5 style.

--HG--
extra : convert_revision : 57b853002bc3c9911e122599d9062b41a06d8e6a
2005-12-23 13:32:31 -05:00
Kevin Lim
6da93ea526 Apply patch for syscall emulation provided by Antti Miettinen (apm@brigitte.dna.fi). It provides support for more syscalls in syscall emulation mode.
arch/alpha/alpha_linux_process.cc:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Apply patch for syscall emulation provided by Antti Miettinen (apm@brigitte.dna.fi).

--HG--
extra : convert_revision : 37fbc78a927110b7798343afd2c5f37a269e42b4
2005-11-22 12:08:08 -05:00
Nathan Binkert
0dcb288365 Cleanup the StackTrace interfaces and profile interfaces so they
are more efficient and reduce the number of new/delete calls

arch/alpha/stacktrace.cc:
    - Change the StackTrace code so that the class can more easily be
    cleaned out and reused to avoid extra allocations.
    - Allow trace() to accept a static instruction pointer so it can
    determine if the instruction is worth tracing.  This is moved from
    the CPU.
    - provide constants for special meaning PCs (user, console, unknown),
    instead of magic numbers
    - switch to using kernelSymtab instead of allSymtab which will be
    going away
    - if the stack adjustment doesn't make any sense, exit and push
    unknown so we don't get into an infinite loop or record garbage.
    - check to see if we've made too many iterations through the stack
    and panic to avoid an infinite loop
arch/alpha/stacktrace.hh:
    - Change the StackTrace code so that the class can more easily be
    cleaned out and reused to avoid extra allocations.
    - Allow trace() to accept a static instruction pointer so it can
    determine if the instruction is worth tracing.  This is moved from
    the CPU.
    - provide constants for special meaning PCs (user, console, unknown),
    instead of magic numbers
cpu/base.cc:
    only clear the profile if we have one
    include profile.hh here since base.hh doesn't do it anymore
cpu/base.hh:
    no need to include cpu/profile.hh here
cpu/profile.cc:
    use ProfileNode pointers instead of objects in the ChildList
    Consume a vector of addresses since that's really all we
    care about.
cpu/profile.hh:
    Keep pointers to ProfileNodes to reduce the size of these structures
    keep a StackTrace around so that we may reuse it.
    provide consume functions that use the new StackTrace trace interface
    one consume function is inline and tries to fastpath the no trace
    condition, it calls the outlined consume function if a trace is generated.
cpu/simple/cpu.cc:
    include cpu/profile.hh here since base.hh no longer does
    use the new FunctionProfile::consume interface
    (which contains the tracing functions)

--HG--
extra : convert_revision : 5a1d9265289a75f67a497b322926be1f8c2d8eb3
2005-11-20 17:44:58 -05:00
Ali Saidi
ccae5838fd add symbol opcode
--HG--
extra : convert_revision : e050d2c4fec33c41ac21b6f17b3be329b9521429
2005-11-19 01:25:34 -05:00
Steve Reinhardt
e701cf48d9 A couple of FP-related fixes (prompted by Adam having trouble
running SPEC FP codes).

arch/alpha/isa_desc:
    Don't warn about non-standard trapping modes more than
    once per static instruction.  (Had the flag to suppress
    these but forgot to check it!)
build/SConstruct:
    Add USE_SSE2 option to enable compiling w/SSE2 (important
    for getting IEEE-compliant FP on x86).

--HG--
extra : convert_revision : eac69efb28cce7b48035480d8b7cb004782969f4
2005-11-09 09:52:07 -05:00
Nathan Binkert
e999645caf define a couple more abi regiesters
--HG--
extra : convert_revision : 2b909cc784d4fdd4833a70e86d13c207a7c1dd23
2005-10-18 20:02:23 -04:00
Nathan Binkert
a81c03737a Add new function profiling stuff, wrap the pc_sample stuff into it.
SConscript:
    Get rid of the pc_sample stuff and move to the new profiling stuff
base/traceflags.py:
    DPRINTF Stack stuff
cpu/base.cc:
cpu/base.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
    Add profiling stuff
kern/kernel_stats.hh:
    Use a smart pointer
sim/system.cc:
sim/system.hh:
    Create a new symbol table that has all of the symbols for a
    particular system
util/stats/categories.py:
    change around the categories, add categories for function
    profiling stuff
util/stats/profile.py:
    No profile parsing and display code to deal with function
    profiling stuff, graph, dot, and text outputs.

--HG--
extra : convert_revision : b3de0cdc8bd468e42647966e2640ae009bda9eb8
2005-10-18 19:07:42 -04:00
Steve Reinhardt
310f608757 Clean up indentation in isa_desc.
arch/alpha/isa_desc:
    Little bit of re-ordering and indentation clean-up.

--HG--
extra : convert_revision : e538ff89d8b507c3e1aa68a032578fcaa645d7ee
2005-09-24 18:17:51 -04:00