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Author SHA1 Message Date
Ali Saidi 969688154d Simpoints: Fix regression bug/Don't set process.simpoint, if simpoint doesn't exist 
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extra : convert_revision : c156c49668815755c4c788f807e8eba32151aa24
 2008-03-15 22:20:09 -04:00
Gabe Black 50946b1673 Merge 
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extra : convert_revision : ec5f41b2007ade15f6f4c4a1533e50f9cba2798e
 2008-03-06 21:09:15 -05:00
Gabe Black a245b0eedf X86: Refine the local APIC. 
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extra : convert_revision : 2789c54ed555fed2f2a333fcc7dc6454f294ebf2
 2008-03-06 20:37:28 -05:00
Vilas Sridharan 21fd15ad9a O3CPU: Don't call dumpInsts if DEBUG is not defined 
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extra : convert_revision : 3194bde4c624d118969bfbf92282539963a72245
 2008-03-06 00:27:09 -05:00
Gabe Black 66aaabf4ae X86: Don't map the local APIC into the physical address space in SE mode. 
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extra : convert_revision : b7103974b12130bbf43583c4cb5294b808add208
 2008-03-01 00:05:12 -05:00
Ali Saidi 65332ef3a9 Added tag m5_2.0_beta4 for changeset cad8c2b5d2ec 
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extra : convert_revision : 3012e3c0393b8fd2f83e3532172269a27c0bbb04
 2008-02-29 18:08:49 -05:00
Ali Saidi ead7dd4bb1 Added tag m5_2.0_beta5 for changeset fb826c79a385 
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extra : convert_revision : 13e2a028aaf899e2f314e6053266168b274e20fd
 2008-02-29 17:59:45 -05:00
Lisa Hsu 02a56d8d01 Error out if -s is used without --caches (instead of saying you must specify a 
CPU).

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extra : convert_revision : a3b2bfbe7e037146ac08dd08834bf255da692506
 2008-02-29 01:49:36 -05:00
Ali Saidi 0273533adb Configs: Make sure options don't conflict 
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extra : convert_revision : dc9b91cf1d8e33c5e68d7faeb45dbe3e7038d14c
 2008-02-29 01:23:18 -05:00
Ali Saidi 3cb7df428c Configs: Fix some bugs we introduced in the simpoints code 
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extra : convert_revision : ef22c11cb3242903a484fc05dc0f96d3e5f9af72
 2008-02-28 20:39:01 -05:00
Steve Reinhardt 19dfde2317 Automated merge with ssh://daystrom.m5sim.org//repo/m5 
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extra : convert_revision : f4bcd342e7abb86ca83840b723e6ab0b861ecf5b
 2008-02-27 18:18:56 -05:00
Steve Reinhardt 2f41006e44 Update outputs for quick tests to reflect fixed cache stats. 
Will update long tests later.

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extra : convert_revision : 79f66b5761a574f0c8049c1c771c353b42942993
 2008-02-27 18:17:37 -05:00
Korey Sewell 8fb74c238c Add comments in code to describe bug conditions. 
This should help if somebody gets to the bug
fix before me (or someone else)...

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extra : convert_revision : 0ae64c58ef4f7b02996f31e9e9e6bfad344719e2
 2008-02-27 17:50:29 -05:00
Korey Sewell b45cf21a8e Fix Load/Store Queue squashing after a SMT thread is removed but ensuring 
you are squashing from the current instruction # causing the thread exit.

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extra : convert_revision : ccbeece7dd1d5fee43f30ab19370908972113473
 2008-02-27 16:53:08 -05:00
Korey Sewell 34715cc691 Fix offset in removeThread() function so that float registers start freeing up 
from the right point (#32 usually) instead of restarting at 0 and double-freeing.

Commented out assert line in free_list.hh that will check for when double-free condition
goes bad.

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extra : convert_revision : 08d5f9b6a874736e487d101e85c22aaa67bf59ae
 2008-02-27 16:48:33 -05:00
Steve Reinhardt e6d6adc731 Revamp cache timing access mshr check to make stats sane again. 
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extra : convert_revision : 37009b8ee536807073b5a5ca07ed1d097a496aea
 2008-02-26 22:03:28 -08:00
Rick Strong fcfc8b8c4f Configs: Make using Simpoints easier with some config files that support them easily 
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extra : convert_revision : 0f21829306eb68b332f03da410e6c341c8595bdd
 2008-02-27 00:35:09 -05:00
Gabe Black 43ecce5fda X86: Put in initial implementation of the local APIC. 
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extra : convert_revision : 1708a93d96b819e64ed456c75dbb5325ac8114a8
 2008-02-26 23:39:53 -05:00
Gabe Black 98d2ca403e X86: Implement the INVLPG instruction and the TIA microop. 
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extra : convert_revision : 31db1ee082f6c3ca5443cba1eb335e408661ead2
 2008-02-26 23:39:22 -05:00
Gabe Black 8b4796a367 TLB: Make a TLB base class and put a virtual demapPage function in it. 
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extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
 2008-02-26 23:38:51 -05:00
Gabe Black 7bde0285e5 X86: Get PCI config space to work, and adjust address space prefix numbering scheme. 
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extra : convert_revision : 2b382f478ee8cde3a35aa4c105196f200bc7afa6
 2008-02-26 23:38:01 -05:00
Steve Reinhardt bdf3323915 Cache: better comments particularly regarding writeback situation. 
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extra : convert_revision : 59ff9ee63ee0fec5a7dfc27b485b737455ccf362
 2008-02-26 20:17:26 -08:00
Ali Saidi 8c0baf2ce4 Update make release, README, and RELEASE_NOTES for b5 
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extra : convert_revision : a4958e934f599bff24b251507da7c266c89430fc
 2008-02-26 17:28:31 -05:00
Gabe Black 8833b4cd44 Bus: Update the stats for the recent bus fix. 
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extra : convert_revision : dc29f7b5e6fa30a50305193cb0e5aed942f7e407
 2008-02-26 02:20:40 -05:00
Gabe Black ec1a4cbbc7 Bus: Fix the bus timing to be more realistic. 
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extra : convert_revision : acd70dc98ab840e55b114706fbb6afb2a95e54bc
 2008-02-26 02:20:08 -05:00
Vilas Sridharan 2e079ce038 add instruction count fast forwaing and max instruction options 
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extra : convert_revision : 8fe45e512229cdc3e0dcd23e3e5c54516c445d0f
 2008-02-22 17:48:10 -05:00
Stephen Hines ceee3ba96e Added ARM_SE as a build option. 
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extra : convert_revision : 905e3acfa58bd14f8101e29dadc0de71d23a79cc
 2008-02-19 16:42:32 -05:00
Steve Reinhardt 3204f96809 Update stats for new writeback behavior. 
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extra : convert_revision : 3e932b5773f5fb9a119822d5bf497f61e9409c14
 2008-02-16 14:58:37 -05:00
Steve Reinhardt 4597a71cef Make L2+ caches allocate new block for writeback misses 
instead of forwarding down the line.

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extra : convert_revision : b0d6e7862c92ea7a2d21f817d30398735e7bb8ba
 2008-02-16 14:58:03 -05:00
Steve Reinhardt 69ce7f953b Update stats for some unknown minor x86 changes 
(assuming someone just forgot to do this... tsk tsk).

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extra : convert_revision : 303d7bbf5e2c892d5f4498a9de2e2b82496ccd0e
 2008-02-16 13:53:12 -05:00
Ali Saidi 9faec83ac5 CPU: move the PC Events code to a place where the code won't be executed multiple times if an instruction faults. 
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extra : convert_revision : 19c8e46a4eea206517be7ed4131ab9df0fe00e68
 2008-02-14 16:14:35 -05:00
Ali Saidi fc38e9c630 Configs: Change Simulation.py to return a subclass of the CPU models rather than the original class. Without this changes elsewhere in the config script (e.g. the DriveSys frequency can change the TestSys frequency. 
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extra : convert_revision : f972207c616590a60a6e103daa5de469cf124b44
 2008-02-14 16:13:50 -05:00
Ali Saidi a33a3f7c55 Update copyright dates 
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extra : convert_revision : 547e7ddff6b8005a9eaad60970bc51984e84fcd1
 2008-02-11 12:35:28 -05:00
Steve Reinhardt 71835d42df Automated merge with file:/home/stever/hg/m5-orig 
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extra : convert_revision : 86a55cd98a9704f756a70aa0cbd2820cf92c821d
 2008-02-11 08:31:26 -08:00
Steve Reinhardt 2f7421b12b EXTRAS now points to src instead of needing 'src' subdir. 
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extra : convert_revision : 8e7e4516ace8c7852eeea3c479bfd567839a8061
 2008-02-11 08:04:01 -08:00
Steve Reinhardt 476a2ee950 Wait to set BUILD_DIR until *after* env is copied. 
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extra : convert_revision : 03153e7aaa1fb2a435900eab08a98ec1a6ce62db
 2008-02-11 07:47:44 -08:00
Nicolas Zea 4c7eb21119 Bus: Only update port cache when there is an item to update it with. 
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extra : convert_revision : 84848fd48bb9e6693a0518c862364142b1969aa8
 2008-02-10 19:41:03 -05:00
Ali Saidi d167e2bb97 IGbE: Fix a couple of bugs. 
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extra : convert_revision : a1f16bd82b6fbd5b6b5dc0f08b9e69858bea86ca
 2008-02-10 19:32:12 -05:00
Steve Reinhardt 9d7a69c582 Fix #include lines for renamed cache files. 
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extra : convert_revision : b5008115dc5b34958246608757e69a3fa43b85c5
 2008-02-10 14:45:25 -08:00
Steve Reinhardt d56e77c180 Rename cache files for brevity and consistency with rest of tree. 
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rename : src/mem/cache/base_cache.cc => src/mem/cache/base.cc
rename : src/mem/cache/base_cache.hh => src/mem/cache/base.hh
rename : src/mem/cache/cache_blk.cc => src/mem/cache/blk.cc
rename : src/mem/cache/cache_blk.hh => src/mem/cache/blk.hh
rename : src/mem/cache/cache_builder.cc => src/mem/cache/builder.cc
rename : src/mem/cache/miss/mshr.cc => src/mem/cache/mshr.cc
rename : src/mem/cache/miss/mshr.hh => src/mem/cache/mshr.hh
rename : src/mem/cache/miss/mshr_queue.cc => src/mem/cache/mshr_queue.cc
rename : src/mem/cache/miss/mshr_queue.hh => src/mem/cache/mshr_queue.hh
rename : src/mem/cache/prefetch/base_prefetcher.cc => src/mem/cache/prefetch/base.cc
rename : src/mem/cache/prefetch/base_prefetcher.hh => src/mem/cache/prefetch/base.hh
rename : src/mem/cache/prefetch/ghb_prefetcher.cc => src/mem/cache/prefetch/ghb.cc
rename : src/mem/cache/prefetch/ghb_prefetcher.hh => src/mem/cache/prefetch/ghb.hh
rename : src/mem/cache/prefetch/stride_prefetcher.cc => src/mem/cache/prefetch/stride.cc
rename : src/mem/cache/prefetch/stride_prefetcher.hh => src/mem/cache/prefetch/stride.hh
rename : src/mem/cache/prefetch/tagged_prefetcher.cc => src/mem/cache/prefetch/tagged.cc
rename : src/mem/cache/prefetch/tagged_prefetcher.hh => src/mem/cache/prefetch/tagged.hh
rename : src/mem/cache/tags/base_tags.cc => src/mem/cache/tags/base.cc
rename : src/mem/cache/tags/base_tags.hh => src/mem/cache/tags/base.hh
rename : src/mem/cache/tags/Repl.py => src/mem/cache/tags/iic_repl/Repl.py
rename : src/mem/cache/tags/repl/gen.cc => src/mem/cache/tags/iic_repl/gen.cc
rename : src/mem/cache/tags/repl/gen.hh => src/mem/cache/tags/iic_repl/gen.hh
rename : src/mem/cache/tags/repl/repl.hh => src/mem/cache/tags/iic_repl/repl.hh
extra : convert_revision : ff7a35cc155a8d80317563c45cebe405984eac62
 2008-02-10 14:15:42 -08:00
Stephen Hines 6cc1573923 Make the Event::description() a const function 
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extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
 2008-02-06 16:32:40 -05:00
Stephen Hines 0ccf9a2c37 Add base ARM code to M5 
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extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af
 2008-02-05 23:44:13 -05:00
Steve Reinhardt b96631e1a0 Cleaned up os.path imports a bit. 
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extra : convert_revision : ee75bf9abd249ab053e804739cc50972475cd5b6
 2008-02-05 17:43:45 -08:00
Steve Reinhardt d725ff450d Make EXTRAS work for SConsopts too. 
Requires pushing source files down into 'src' subdir relative
to directory listed in EXTRAS.

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extra : convert_revision : ca04adc3e24c60bd3e7b63ca5770b31333d76729
 2008-02-05 17:40:08 -08:00
Gabe Black ca313e2303 X86: Put an SMBios/DMI table in memory. 
This is basically just the header right now, but there's an untested
mechanism in place to fill out the table and make sure everything is
updated correctly.

--HG--
extra : convert_revision : c1610c0dfa211b7e0d091a04133695d84f500a1c
 2008-01-23 15:28:54 -05:00
Gabe Black 423bbe6499 X86: Optomize the bit scanning instruction microassembly a little. More can be done. 
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extra : convert_revision : 3cf6e972f0e41e3529a633ecbb31289e1bd17f0f
 2008-01-23 08:18:27 -05:00
Gabe Black 60c2d98fc0 X86: Implement and attach the BSR and BSF instructions. 
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extra : convert_revision : be7e11980092e5d1baff0e05d4ec910305966908
 2008-01-22 00:10:33 -05:00
Gabe Black f809637011 X86: Fill out group17 in the decoder. 
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extra : convert_revision : 66ab9c0fc3086f66e3d6d82d47964ecf406c3a8a
 2008-01-21 16:27:40 -05:00
Gabe Black 657b52fea1 X86: Use the existing boot_osflags instead of duplicating it. 
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extra : convert_revision : e04e438d7d261a61c52b946c23cd126ed648814a
 2008-01-21 04:32:34 -05:00
Ali Saidi 48295aa514 Update long o3 regressions for o3 change in previous changeset 
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extra : convert_revision : 00242105076eb4466cce21038858f2b9d20b2fe2
 2008-01-16 11:11:55 -05:00