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Author SHA1 Message Date
Ali Saidi
e9ddc7fbca Regression: fix configuration for SPARC_FS 
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extra : convert_revision : 88aa9649cc1b4d8165616e98880d3d6cd2a75762
 2007-08-12 19:44:04 -04:00
Ali Saidi
d114e5fae6 Regression: Update stats for cache changes. 
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extra : convert_revision : 005672e722dec00cb4c38501b5189b4eb7515ca1
 2007-08-12 19:43:55 -04:00
Ali Saidi
02353a60ee MemorySystem: Fix the use of ?: to produce correct results. 
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extra : convert_revision : 31aad7170b35556a4c984f4ebc013137d55d85eb
 2007-08-12 19:43:54 -04:00
Nathan Binkert
64295b800f merge 
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extra : convert_revision : 5866eaa4008c4fa5da7fbb443132b8326955f71d
 2007-08-12 09:56:37 -07:00
Nathan Binkert
b92594dd90 style: If IGNORE_STYLE=True is set on the scons command line, ignore style. 
Use this in the regress script to avoid issues with the checker.

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extra : convert_revision : 562b6a6d73dc46e412d00ba2588af2793335274e
 2007-08-12 09:56:05 -07:00
Vincentius Robby
ec4000e0e2 Added fastmem option. 
Lets CPU accesses to physical memory bypass Bus.

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extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c
 2007-08-08 18:43:12 -04:00
Vincentius Robby
1caed14654 alpha: Quick fix for things related to TLB MRU cache. 
simple-timing test for ALPHA_FS breaks.

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extra : convert_revision : 5a1b05cddd480849913da81a3b3931fec16485a8
 2007-08-08 18:38:19 -04:00
Ali Saidi
9493501fdb Regression: Add an I/O Cache to the full system regressions that have a cache. 
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extra : convert_revision : 8ba96e21be2f602eed8258d410038dbe998ef176
 2007-08-10 16:14:02 -04:00
Ali Saidi
06a9f58c68 DMA: Add IOCache and fix bus bridge to optionally only send requests one 
way so a cache can handle partial block requests for i/o devices.

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extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
 2007-08-10 16:14:01 -04:00
Ali Saidi
5c38668ed6 Bus: Only call end() on an stl object once in a loop 
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extra : convert_revision : 238dcd6da7577b533e52ada2107591c4e9168ebd
 2007-08-10 16:14:01 -04:00
Vincentius Robby
3d40cba8d4 Port, StaticInst: Revert unnecessary changes. 
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extra : convert_revision : e6ef262bbbc5ad53498e55caac1897e6cc2a61e6
 2007-08-08 14:54:02 -04:00
Vincentius Robby
13d10e844c alpha: Make the TLB cache to actually work. 
Improve MRU checking for StaticInst, Bus, TLB

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extra : convert_revision : 9116b5655cd2986aeb4205438aad4a0f5a440006
 2007-08-08 14:18:09 -04:00
Gabe Black
ef32494e72 Alpha: Fix an off by one error with the tlb caching mechanism. 
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extra : convert_revision : e17f7a0d58a2e59b2e270f0827db33d0a29365e0
 2007-08-07 21:51:12 -07:00
Gabe Black
0fd999ca40 Merge with head. 
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extra : convert_revision : ae7b3df573368c29a66d5b027ecad9ffb3a99104
 2007-08-07 15:31:36 -07:00
Gabe Black
e85144bff2 Statetrace: Make statetrace do string instructions all at once like m5 does. 
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extra : convert_revision : 2103029077450e46f70077066708255310963d9d
 2007-08-07 15:27:54 -07:00
Gabe Black
cd3f0646ca X86: Added some missing parenthesis in the condition code calculation function. 
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extra : convert_revision : 663021070a4bcc795bb44e1839b8bcec686a42f0
 2007-08-07 15:26:50 -07:00
Gabe Black
24541780c6 X86: Implemented and hooked in SCAS (scan string) 
Fixed the asz assembler symbol.
Adjusted the condion checks to have appropriate options.
Implemented the SCAS microcode.
Attached SCAS into the decoder.

--HG--
extra : convert_revision : 17bf9ddae6bc2069e43b076f8f83c4e54fb7966c
 2007-08-07 15:25:41 -07:00
Gabe Black
d79a591608 X86: Add a format to handle string instructions which can use the repe and repne prefixes. 
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extra : convert_revision : 205fbbb947258bc0ef2915e22d5b32a3df1a1ce2
 2007-08-07 15:23:01 -07:00
Gabe Black
60c61cb2b1 X86: Overhaul of ruflags to get it to work correctly. 
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extra : convert_revision : 00a36a80a1945806aac9fa7d9d6a3906465dcad2
 2007-08-07 15:21:13 -07:00
Gabe Black
fb6cdf09cb X86: Make a microcode branch microop. 
Also some touch up for ruflag.

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extra : convert_revision : 829947169af25ca6573f53b9430707101c75cc23
 2007-08-07 15:19:26 -07:00
Gabe Black
cae8d20633 Merge with head. 
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extra : convert_revision : 3edb9f03353b18b4c9f062bccf11e79cfb3c15f2
 2007-08-04 20:27:23 -07:00
Gabe Black
30e777a5d3 X86: Implement microops and instructions that manipulate the flags register. 
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extra : convert_revision : 566841577bf4a98cac0b65292fe0f7daf89a9203
 2007-08-04 20:24:18 -07:00
Gabe Black
802f13e6bd X86: Make 64 bit unaligned accesses work as well as the other sizes. 
There is a fundemental flaw in how unaligned accesses are supported, but this
is still an improvement.

--HG--
extra : convert_revision : 1c20b524ac24cd4a812c876b067495ee6a7ae29f
 2007-08-04 20:22:20 -07:00
Gabe Black
b9793c2506 X86: Make the open flags correct. 
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extra : convert_revision : 2dc81345176d1de247a567d1f748e2b2bd05f829
 2007-08-04 20:18:20 -07:00
Gabe Black
fc6b2cceb4 X86: Make fixed register operands ignore register index extensions from the REX prefix. 
The only cases where this was the correct behavior are now handled with the
"B" operand type, and doing things this way was breaking some instructions,
notably a shift.

--HG--
extra : convert_revision : 072346d4f541edaceba7aecc26ba8d2cd756e481
 2007-08-04 20:17:31 -07:00
Gabe Black
6f3bb03a3f X86: Implement the cmpxchg instruction. 
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extra : convert_revision : b9e172bcb9551edf65c63f26dfa07d771edf3e1e
 2007-08-04 20:15:27 -07:00
Gabe Black
e410a925df X86: Start implementing segmentation support. 
Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.

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extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9
 2007-08-04 20:12:54 -07:00
Gabe Black
ced6cbcccf X86: Create a base enum value for indexing into a region of the miscregs. 
This lets you index into a group of registers without having to know
explicitly which one is the lowest in that group.

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extra : convert_revision : e3cad25a1c5910955204c37177b049ca9834cfd9
 2007-08-04 20:07:42 -07:00
Gabe Black
0e6be2a9b1 X86: Add the arch_prctl system call and fix up some microcoding. 
The arch_prctl system call is used to set and get the FS and GS segment
bases. The FS segment is use for TLS, so glibc needs to be able to set it
up.

--HG--
extra : convert_revision : 79501491a15967a7a862add846ff88a934fb1b37
 2007-08-04 20:02:41 -07:00
Nathan Binkert
df015f17a4 switching: turn on profiling after a switch if there's an event 
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extra : convert_revision : 689e5b85c47bb2aaceb7eb38c2a24a2e5b69376c
 2007-08-04 16:11:11 -07:00
Nathan Binkert
7a996ccc98 switching: Remove the drain and resume code from the switching code. 
This allows us to change memory modes as well.
Clean up the code while we're at it.

--HG--
extra : convert_revision : fc5fee9ffd08b791f0607ee2688f32aa65d15354
 2007-08-04 16:09:24 -07:00
Nathan Binkert
5a27431b96 python: use the enum values in the memory mode changing code 
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extra : convert_revision : 2e399b2b407922ad076f93d33af73e3ba4c05218
 2007-08-04 16:06:19 -07:00
Nathan Binkert
300712c0d1 swig: %include all of the enums to get all of the definitions. 
(instead of %import)

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extra : convert_revision : bc4a39d7be3aad59b34d55aa8dd2c28285f09db9
 2007-08-04 16:05:18 -07:00
Nathan Binkert
5364d109d2 merge 
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extra : convert_revision : 5390fef726afe14a89f1f36512239f72563557e2
 2007-08-04 16:03:18 -07:00
Nathan Binkert
157bd25802 python: provide access to stats 
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extra : convert_revision : 18a4e9ef21bd77ec73482557e028d535f0c1f273
 2007-08-04 16:02:04 -07:00
Nathan Binkert
d8900d8478 main: return an an exit code of 1 when we exit due to a python exception. 
This requires us to not use PyRun_SimpleString, but PyRun_String since the
latter actually returns a result

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extra : convert_revision : 3e3916ddd7eef9957569d8e72e73ba4c3160ce20
 2007-08-04 16:00:36 -07:00
Nathan Binkert
e8e1ddd530 SimpleCPU: Add some DPRINTFs 
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extra : convert_revision : 5fdd5a9595c3e5d6ce5f9e8c9af0a8e6c857551c
 2007-08-04 15:56:48 -07:00
Vincentius Robby
1db9e1fb8f port: Implement cache for port interfaces and ranges 
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extra : convert_revision : d7cbec7c277fb8f4d8846203caae36ce629602d5
 2007-08-04 16:05:55 -04:00
Vincentius Robby
2898d76827 alpha: Implement a cache for recently used page table entries 
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extra : convert_revision : 1bb80d71fa91e500a68390e5dc17464ce7136fba
 2007-08-04 14:25:35 -04:00
Vincentius Robby
acac5580f2 StaticInst: Fix decode cache initialization. Cache functionality was negated. 
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extra : convert_revision : fe313718dba8236f3e9bceb49f8c5efccfc06a06
 2007-08-04 14:25:17 -04:00
Steve Reinhardt
c2b533cc3b Add cscope files to .hgignore. 
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extra : convert_revision : 82598579baf50cd258714c7e533b96bc6bd1305a
 2007-08-03 16:27:51 -07:00
Steve Reinhardt
bb3f7dc83b tests: new ref outputs for new cache model 
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extra : convert_revision : 244749072f97e425c2ca1cf296f2b95f37e99eb6
 2007-08-03 18:04:30 -04:00
Steve Reinhardt
851e3c852b tests: replace all dest ref files on upgrade (if possible). 
Originally we were copying all source files in, but this caused
problems when (large) inputs were copied along with outputs.
Then we switched to just copying the standard files (m5stats.txt,
etc.) but that was missing things like the *.console files.
This fix should catch all the non-standard files too as long as
they are copied in manually once when the test is set up.
Also get a lot nicer about warning when files are ignored,
and warn when expected files are missing.
Those new Python sets sure are handy.

--HG--
extra : convert_revision : 55c046de124522499af74a471968677c020bbf38
 2007-08-03 18:04:26 -04:00
Steve Reinhardt
a0bf2535a8 tests: config.out no longer exists, eliminate ref copy. 
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extra : convert_revision : e2d6aa61aa2ffd1a9d16260244512eeb1fe4d5a3
 2007-08-03 18:03:59 -04:00
Steve Reinhardt
3afc625975 merge from head 
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extra : convert_revision : 21f7afe2719c00744c0981212c1ee6e442238e01
 2007-08-03 03:51:30 -04:00
Steve Reinhardt
62aa1d7f55 cache: get rid of obsolete params from python. 
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extra : convert_revision : cd40e0ef938ef6da1cccedf7be01c3ac5b4883fb
 2007-08-03 03:51:13 -04:00
Gabe Black
121a894ce0 Merge with head. 
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extra : convert_revision : c8b066289916b3fb24bcae1e9c76e27ad4cf61b1
 2007-08-02 23:30:25 -07:00
Nathan Binkert
0536d0cde9 python: Improve support for python calling back to C++ member functions. 
Add support for declaring SimObjects to swig so their members can be wrapped.
Make sim_object.i only contain declarations for SimObject.
Create system.i to contain declarations for System.
Update python code to properly call the C++ given the new changes.

--HG--
extra : convert_revision : 82076ee69e8122d56e91b92d6767e356baae420a
 2007-08-02 22:50:02 -07:00
Ali Saidi
dc7a38dce7 Merge: No changes 
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extra : convert_revision : ee56f958f6b295571cf881b81380cfba3d4ce02e
 2007-08-02 22:09:54 -04:00
Ali Saidi
50bceeae14 Serialize: This shouldn't have been commited, I got a little bit carried away it seems. 
--HG--
extra : convert_revision : f8d4d9f3d395d2d3db020cd016c7840876097791
 2007-08-02 22:08:33 -04:00