X86: Implement microops and instructions that manipulate the flags register.

--HG--
extra : convert_revision : 566841577bf4a98cac0b65292fe0f7daf89a9203
This commit is contained in:
Gabe Black 2007-08-04 20:24:18 -07:00
parent 802f13e6bd
commit 30e777a5d3
6 changed files with 47 additions and 23 deletions

View file

@ -529,13 +529,13 @@
}
}
0x1F: decode OPCODE_OP_BOTTOM3 {
0x0: clc();
0x1: stc();
0x2: cli();
0x3: sti();
0x4: cld();
0x5: std();
format Inst {
0x0: CLC();
0x1: STC();
0x2: WarnUnimpl::cli();
0x3: WarnUnimpl::sti();
0x4: CLD();
0x5: STD();
//0x6: group4();
0x6: decode MODRM_REG {
0x0: INC(Eb);

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@ -53,18 +53,39 @@
#
# Authors: Gabe Black
microcode = ""
microcode = '''
def macroop CLD {
ruflags t1
limm t2, "~((uint64_t)DFBit)"
and t1, t1, t2
wruflags t1, t0
};
def macroop STD {
ruflags t1
limm t2, "DFBit"
or t1, t1, t2
wruflags t1, t0
};
def macroop CLC {
ruflags t1
andi t2, t1, "CFBit"
wruflags t1, t2
};
def macroop STC {
ruflags t1
ori t1, t1, "CFBit"
wruflags t1, t0
};
def macroop CMC {
ruflags t1
wruflagsi t1, "CFBit"
};
'''
#let {{
# class CLC(Inst):
# "GenFault ${new UnimpInstFault}"
# class CMC(Inst):
# "GenFault ${new UnimpInstFault}"
# class STC(Inst):
# "GenFault ${new UnimpInstFault}"
# class CLD(Inst):
# "GenFault ${new UnimpInstFault}"
# class STD(Inst):
# "GenFault ${new UnimpInstFault}"
# class CLI(Inst):
# "GenFault ${new UnimpInstFault}"
# class STI(Inst):

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@ -80,12 +80,6 @@ def macroop CMPXCHG_P_R {
};
'''
#let {{
# class CMPXCHG(Inst):
# "GenFault ${new UnimpInstFault}"
# class CMPXCHG8B(Inst):
# "GenFault ${new UnimpInstFault}"
# class CMPXCHG16B(Inst):
# "GenFault ${new UnimpInstFault}"
# class XADD(Inst):
# "GenFault ${new UnimpInstFault}"
# class XCHG(Inst):

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@ -615,8 +615,12 @@ let {{
''')
defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;")
defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2')
defineMicroRegOpRd('Rdip', 'DestReg = RIP')
defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits')
defineMicroRegOpImm('Ruflag', 'DestReg = bits(ccFlagBits, imm8);', \
flagCode = genCCFlagBitsLogic)
defineMicroRegOpImm('Sext', '''
IntReg val = psrc1;

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@ -176,6 +176,10 @@ let {{
# Non register modrm settings should cause an error
env.addReg(ModRMRMIndex)
Name += "_R"
elif opType.tag in ("X", "Y"):
# This type of memory addressing is for string instructions.
# They'll use the right index and segment internally.
Name += "_M"
else:
raise Exception, "Unrecognized tag %s." % opType.tag

View file

@ -70,6 +70,7 @@ namespace X86ISA
EZFBit = 1 << 5,
ZFBit = 1 << 6,
SFBit = 1 << 7,
DFBit = 1 << 10,
OFBit = 1 << 11
};