Commit graph

61 commits

Author SHA1 Message Date
Nathan Binkert
8522474318 Merge zizzer.eecs.umich.edu:/bk/m5
into crampon.my.domain:/z/binkertn/research/m5/head

--HG--
extra : convert_revision : eb0e28e22549f875cef25043491a30c2755676ed
2005-06-05 02:26:18 -04:00
Steve Reinhardt
d4559c32e4 Add licenses in python dir.
python/m5/__init__.py:
python/m5/convert.py:
python/m5/multidict.py:
python/m5/smartdict.py:
    Add license.

--HG--
extra : convert_revision : 825dcad94e13b18aadc7188053ad1999a0219eae
2005-06-05 01:57:57 -04:00
Nathan Binkert
3e5e3e2d28 make all of the turbolaser stuff only compile if ALPHA_TLASER
is defined.

build/SConstruct:
    Default ALPHA_TLASER to false
dev/uart8250.cc:
    fix paths

--HG--
extra : convert_revision : 3616b5b4b9060860a73568a4ed4f1e8eb991938f
2005-06-05 01:24:17 -04:00
Ali Saidi
adce616cfe split uart into urt8250 and uart8530
fix some doxygen comments

SConscript:
    Added split uart files
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/tsunami.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/tsunamireg.h:
    fix doxgyen file comment
dev/uart.cc:
dev/uart.hh:
python/m5/objects/Uart.py:
    split uart into urt8250 and uart8530

--HG--
extra : convert_revision : 2e70aad892a37620d7909017648bca6d7d69d678
2005-06-05 01:22:21 -04:00
Nathan Binkert
b46730c7ec BaseSystem -> System
Make System an object that can be instantiated.  For operating
systems that don't need any OS specific hacks.

python/m5/objects/AlphaConsole.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/Tsunami.py:
    BaseSystem -> System

--HG--
rename : python/m5/objects/BaseSystem.py => python/m5/objects/System.py
extra : convert_revision : e5d12db02abef1b0eda720b50dd2c09cb1ac5232
2005-06-04 14:19:05 -04:00
Steve Reinhardt
af3add2e33 Bug fix & cleanup in config code.
python/m5/config.py:
    Bug fix: code was silently converting between
    incompatible SimObject types as an unintended
    side-effect of the object cloning support.

--HG--
extra : convert_revision : 236f4fe5370f2eddf8af8fab68e2b83dccc34305
2005-06-03 16:21:37 -04:00
Nathan Binkert
0ee75f27b8 Fix-up some config issues
python/m5/config.py:
    Make NetworkBandwidth and MemoryBandwidth work
python/m5/objects/Ethernet.py:
    Make 1Gbps default for ethernet

--HG--
extra : convert_revision : 59e62f7e62624356ae8d7304598617f60667f040
2005-06-02 11:19:01 -04:00
Steve Reinhardt
8031cd93b5 Standardize clock parameter names to 'clock'.
Fix description for Bus clock_ratio (no longer a ratio).
Add Clock param type (generic Frequency or Latency).

cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/beta_cpu/alpha_full_cpu_builder.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/sinic.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
sim/universe.cc:
    Standardize clock parameter names to 'clock'.
    Fix description for Bus clock_ratio (no longer a ratio).
python/m5/config.py:
    Minor tweaks on Frequency/Latency:
    - added new Clock param type to avoid ambiguities
    - factored out init code into getLatency()
    - made RootFrequency *not* a subclass of Frequency so it
    can't be directly assigned to a Frequency paremeter

--HG--
extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506
2005-06-01 21:44:00 -04:00
Steve Reinhardt
3e7f660401 A few more config updates. Works with regression now.
configs/splash2/run.py:
    Update file for new config changes.
python/m5/config.py:
    - isParamContext() not defined any more
    - fix bug with re-assigning vectors over scalars
    and vice versa

--HG--
rename : configs/splash2/run.mpy => configs/splash2/run.py
extra : convert_revision : 2eb28a92f8de327f6dfddd01467c61e759275f6b
2005-06-01 17:08:45 -04:00
Steve Reinhardt
aad02f8088 Major cleanup of python config code.
Special mpy importer is gone; everything is just plain
Python now (funky, but straight-up).
May not completely work yet... generates identical ini
files for many configs/kernel settings, but I have yet
to run it against regressions.  This commit is for my
own convenience and won't be pushed until more testing
is done.

python/m5/__init__.py:
    Get rid of mpy_importer and param_types.
python/m5/config.py:
    Major cleanup.  We now have separate classes and
    instances for SimObjects.  Proxy handling and param
    conversion significantly reorganized.  No explicit
    instantiation step anymore; we can dump an ini file
    straight from the original tree.
    Still needs more/better/truer comments.
test/genini.py:
    Replace LoadMpyFile() with built-in execfile().
    Export __main__.m5_build_env.
python/m5/objects/AlphaConsole.py:
python/m5/objects/AlphaFullCPU.py:
python/m5/objects/AlphaTLB.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/CoherenceProtocol.py:
python/m5/objects/Device.py:
python/m5/objects/DiskImage.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Ide.py:
python/m5/objects/IntrControl.py:
python/m5/objects/MemTest.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/Platform.py:
python/m5/objects/Process.py:
python/m5/objects/Repl.py:
python/m5/objects/Root.py:
python/m5/objects/SimConsole.py:
python/m5/objects/SimpleDisk.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
    Fixes for eliminating mpy_importer, and modified
    handling of frequency/latency params.
    Also renamed parent to Parent.

--HG--
rename : python/m5/objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.mpy => python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.mpy => python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.mpy => python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.mpy => python/m5/objects/BaseCache.py
rename : python/m5/objects/BaseSystem.mpy => python/m5/objects/BaseSystem.py
rename : python/m5/objects/Bus.mpy => python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.mpy => python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.mpy => python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.mpy => python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.mpy => python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.mpy => python/m5/objects/IntrControl.py
rename : python/m5/objects/MemTest.mpy => python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.mpy => python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.mpy => python/m5/objects/Platform.py
rename : python/m5/objects/Process.mpy => python/m5/objects/Process.py
rename : python/m5/objects/Repl.mpy => python/m5/objects/Repl.py
rename : python/m5/objects/Root.mpy => python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.mpy => python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.py
rename : python/m5/objects/Tsunami.mpy => python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.mpy => python/m5/objects/Uart.py
extra : convert_revision : 9dc55103a6f5b40eada4ed181a71a96fae6b0b76
2005-05-29 01:14:50 -04:00
Kevin Lim
e5721ce677 Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/current/m5
--HG--
extra : convert_revision : c403960153ed648e7da7251465ca9350ba10cd27
2005-05-17 14:34:46 -04:00
Steve Reinhardt
16dcebf4c4 Add mem_trace parameter to BaseCache.
python/m5/objects/BaseCache.mpy:
    Add mem_trace parameter.

--HG--
extra : convert_revision : a0bab53fabd7426eee5ca9c845c02a6ac2e1722f
2005-05-13 15:01:42 -04:00
Kevin Lim
c03e97b62d Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/current/m5
--HG--
extra : convert_revision : b868e7920eaa3682c6123651f0c598673ebb7f22
2005-05-04 14:41:36 -04:00
Kevin Lim
61d95de4c8 Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version.
SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
    Remove OOO CPU stuff.
arch/alpha/faults.hh:
    Add fake memory fault.  This will be removed eventually.
arch/alpha/isa_desc:
    Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
    Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
    Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
    Remove asid.
cpu/beta_cpu/comm.hh:
    Remove global history field.
cpu/beta_cpu/commit.hh:
    Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
    Update some of the full system code so it compiles.  Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
    Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
    Add debug function.
cpu/beta_cpu/decode_impl.hh:
    Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
    Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
    Changed some of the full system code so it compiles.  Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
    Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
    Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
    Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
    New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
    Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
    Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
    Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
    Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
    Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
    Remove OOO CPU stuff.  Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
    Extra forward declares added due to compile error.

--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
2005-05-03 10:56:47 -04:00
Nathan Binkert
364f6e3235 Make sinic work with mpy
dev/sinic.cc:
dev/sinic.hh:
    Fix sinic parameters. (header_bus -> io_bus)
python/m5/objects/Ethernet.mpy:
    Add simobj definitions for sinic.

--HG--
extra : convert_revision : 77d5b80bd1f1708329b263fb48965d7f555cc9d1
2005-05-02 19:00:11 -04:00
Ron Dreslinski
602a489573 Add suport for no allocation of cache block on a dma read passing through a cache from the cpu-side interface
--HG--
extra : convert_revision : 0a3b3741924ed39c1c8710d0963e4c8f3e73f81a
2005-04-29 21:01:43 -04:00
Nathan Binkert
3154e2a0c7 Add the m5 parameter to the ns83820 device model so that we
can pass simulator specific options to the device driver.

dev/ns_gige.cc:
    Add the m5 register and parameter to the ns83820 device model
    so that we can pass simulator specific options to the device
    driver.
dev/ns_gige.hh:
dev/ns_gige_reg.h:
    Add the m5 register to the ns83820 device model

--HG--
extra : convert_revision : 84674887560fa3b607e725b8e5bc8272761fcf09
2005-04-24 21:32:32 -04:00
Steve Reinhardt
535cfaa01e Mostly hacks for multiplying Frequency-type proxies by constants
(plus some small fixes).

python/m5/config.py:
    Hacks to allow multiplication on Frequency/Latency-valued proxies.
    Provide __rmul__ as well as __mul__ on Proxy objects.
test/genini.py:
    Default value for -EFOO should be True not 1 (since 1 is no longer
    convertable to Bool).

--HG--
extra : convert_revision : f8a221fcd9e095fdd7b7db4be0ed0cdcd20074be
2005-04-17 00:41:50 -04:00
Nathan Binkert
5eab6c4b41 Make the notion of a global event tick independent of the actual
CPU cycle ticks.  This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency.  For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.

arch/alpha/ev5.cc:
    The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
    frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
    frequency isn't the cpu parameter anymore, cycleTime is.
    create several public functions for getting the cpu frequency
    and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
    Now that ticks aren't cpu cycles, fixup code to advance
    by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
    Provide a function to get the number of ticks for a given
    number of cycles.
dev/alpha_console.cc:
    Update for changes in the way that frequencies and latencies are
    accessed.  Move some stuff to init()
dev/alpha_console.hh:
    Need a pointer to the system and the cpu to get the frequency
    so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
    Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
    outline the constructor and destructor
dev/platform.hh:
    outline the constructor and destructor.
    don't keep track of the interrupt frequency.  Only provide the
    accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
    outline the constructor and destructor
    Don't set the interrupt frequency here.  Get it from the actual device
    that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
    Make the interrupt interval a configuration parameter.  (And convert
    the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
    For now, we must get the boot cpu's frequency as a parameter
    since allowing the system to have a pointer to the boot cpu would
    cause a cycle.
kern/tru64/tru64_system.cc:
    For now, we must get the boot cpu's frequency as a parameter
    since allowing the system to have a pointer to the boot cpu would
    cause a cycle.
python/m5/config.py:
    Fix support for cycle_time relative latencies and frequencies.
    Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
    All CPUs now have a cycle_time.  The default is the global frequency,
    but it is now possible to set the global frequency to some large value
    (like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
    Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
    We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
    Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
    this frequency isn't needed.  We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
    The clock generator should hold the frequency
sim/eventq.hh:
    Need to remove this assertion because the writeback event
    queue is different from the CPU's event queue which can cause
    this assertion to fail.
sim/process.cc:
    Fix comment.
sim/system.hh:
    Struct member to hold the boot CPU's frequency.
sim/universe.cc:
    remove unneeded variable.

--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 15:32:06 -04:00
Ron Dreslinski
0d2e816a4c Hand merged a this-> statement for gcc3.4
--HG--
extra : convert_revision : 11daa94a0631da5e9c2e4262a448035491dd86e5
2005-04-08 18:26:00 -04:00
Ron Dreslinski
2d2f663d3a Add Parameter to only do prefetch calculations on data accesses not instruction accesses
--HG--
extra : convert_revision : 85c987561a962f21466f0c1bd0473300d341c398
2005-04-08 17:19:56 -04:00
Nathan Binkert
9fead747f5 fix typo in python config stuff
python/m5/config.py:
    fix typo

--HG--
extra : convert_revision : 2208453d93149ba4af140dd78c29be4c4943b397
2005-04-06 18:00:44 -04:00
Nathan Binkert
f3544a13f3 Fix the python NetworkBandwidth conversion function
python/m5/convert.py:
    Fix the NetworkBandwidth conversion function

--HG--
extra : convert_revision : 93d9856fe6b59827c116e15835d2ef51292bd6c4
2005-04-06 17:59:31 -04:00
Nathan Binkert
1ee77fb23e formatting
--HG--
extra : convert_revision : 0b041556222c3892ee72e4d56c8acdda72bfc303
2005-04-06 17:58:57 -04:00
Nathan Binkert
6d412f63a3 Add TcpPort and UdpPort as python types
python/m5/objects/SimConsole.mpy:
    the listener port is a TcpPort

--HG--
extra : convert_revision : c26fdd93d3bc35d9f1563ac1087a7f75471c9020
2005-04-06 17:05:30 -04:00
Nathan Binkert
c82562c740 full_system isn't a useful parameter anymore, get rid of it.
python/m5/objects/Root.mpy:
sim/universe.cc:
util/stats/stats.py:
    full_system isn't a useful parameter

--HG--
extra : convert_revision : 557091be1faa3cf121c55102aba4e6f4c1bd45ef
2005-04-06 16:58:40 -04:00
Ron Dreslinski
1b2c81b9d7 Add more prefetcher support.
SConscript:
    Add GHB prefetcher to build list
python/m5/objects/BaseCache.mpy:
    Add parameters about when to remove prefetches and wether or not to use cpuid to differentiate access patterns

--HG--
extra : convert_revision : 1d3fef21910f2f34b8c28d01b5f6e86eef53357c
2005-04-04 16:25:22 -04:00
Ron Dreslinski
4889d8f788 Added support for multiple prefetch address from single access (depth of prefetch) also added the ability to squash some prefetchs to match the GHB technique
python/m5/objects/BaseCache.mpy:
    Added parameters

--HG--
extra : convert_revision : 92b646eb61455d283a5c2ac0b3f8fbd62e39fb87
2005-04-02 20:36:08 -05:00
Ron Dreslinski
fdceb0f00c Some hand merges
--HG--
rename : objects/BaseCache.mpy => python/m5/objects/BaseCache.mpy
extra : convert_revision : b24ff4c1feb480cf280207d4bbdfe08ef80d1aa2
2005-04-01 19:39:23 -05:00
Nathan Binkert
40bab977bc Better handling of latency/frequency parameter types
python/m5/config.py:
    Addr is slightly different from memory size in that Addr
    will take non strings.
    Deal with the fact that the convert.toFoo functions only accept
    strings.
    Add RootFrequency as a special type for the Root.frequency
    parameter which is not scaled.
    Add ClockPeriod parameter type.
python/m5/convert.py:
    Be more strict about what's allowed.
    Only accept strings as inputs for these conversion functions.
    If the user wants to accept something else, they need to deal
    with the failure and convert other types on their own.
python/m5/objects/Bus.mpy:
    Use the new ClockPeriod parameter type
python/m5/objects/Root.mpy:
    Can't use integers for frequency anymore
python/m5/smartdict.py:
    rename SmartDict.Proxy to just Variable.  Create a new class
    UndefinedVariable that is returned when the user tries to get
    a variable that is not in the dict.  Undefined variable evaluates
    to false, and will cause an error elsewhere.

--HG--
extra : convert_revision : 1d55246fd1af65106f102396234827d6401ef9ce
2005-03-25 22:59:29 -05:00
Nathan Binkert
7e1995a29c Better exceptions in python config
python/m5/config.py:
    Don't raise a new exception, just modify and re-raise the old one.

--HG--
extra : convert_revision : 47f6da3a8cb2ee18a6b400863e7ea80ab0c9a5ea
2005-03-25 22:32:00 -05:00
Nathan Binkert
d10412d565 Improve toBool
python/m5/convert.py:
    an empty string should still be false

--HG--
extra : convert_revision : dd9900794d94cd018b57ec81bcbce1d412e2a83e
2005-03-24 12:24:54 -05:00
Nathan Binkert
eeff53841a Add Frequency and Latency as new parameter types and use them
where we can

python/m5/config.py:
    Add two new parameter types: Frequency and Latency.  These will soon
    be an integral part of the tick is picosecond thing.  If the value
    can be converted directly to an integer without any special tricks,
    we assume that the number is the exact value desired.  Otherwise,
    we convert the number assuming that it is in Hz or s.
python/m5/objects/Bus.mpy:
    Use the new Latency and Frequency types where we can

--HG--
extra : convert_revision : b3cff6020db83fb819507c348451c98697d1cf27
2005-03-24 12:24:17 -05:00
Nathan Binkert
257be74341 Formatting fixes
--HG--
extra : convert_revision : 9a726945b7a1decbecf460df6714257b88742dc8
2005-03-23 22:58:47 -05:00
Nathan Binkert
153130e558 First step in fixing up parameter handling. Clean up the
way ranges work, more fully support metric prefixes for all
integer types, and convert memory sized parameters to the
MemorySize type.

python/m5/config.py:
    - no more _Param and _ParamProxy stuff.  Use the names
    ParamBase and ParamFactory to hopefully make it clearer
    what we intend.
    - Get rid of RangeSize and the old Range class and more fully flesh
    out the Range class to deal with types of parameters and different
    kinds of ranges.
    - Call toInteger on the CheckedInt types so we can use metric prefixes
    in strings for all integers.
    - Get rid of the K, M, and G constants.  Use the proper type or call
    one of the functions in the convert package.
python/m5/convert.py:
    Simple way to deal with both floating point and integer strings.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ethernet.mpy:
    This is a MemorySize typed parameter

--HG--
extra : convert_revision : 92b4ea662d723abdd6c0a49065b79c25400fac9b
2005-03-23 13:25:48 -05:00
Nathan Binkert
48e0b9ed4d style
python/m5/convert.py:
python/m5/smartdict.py:
    follow our naming convention

--HG--
extra : convert_revision : d57a103dfbad1fb6a076bfacdca226c4b1893fb8
2005-03-22 14:51:31 -05:00
Nathan Binkert
ac547c6489 Fix a bug introduced with the multidict commit.
python/m5/config.py:
    search for any base class that is a confignode instead of those
    that derive from param type so that non-type classes work
    too.  (Those that are just derived from ConfigNode and not
    SimObject.)

--HG--
extra : convert_revision : 422181b2e5efd4675ec34adcffecfb58eee0e4e7
2005-03-22 14:47:18 -05:00
Nathan Binkert
5f2b3a6e5d clean up python exceptions
python/m5/config.py:
    clean up exception output a bit.

--HG--
extra : convert_revision : a27e75276ffc9001f44c44595172cf2b455e5e23
2005-03-22 14:42:05 -05:00
Nathan Binkert
3583fb6830 Use the multidict in the python config stuff. Makes code a bit
cleaner.

python/m5/config.py:
    Use the multidict instead of the separately coded _getparam
    and _getvalue stuff.  While we're at it, when we see a default
    parameter, we stick it into the dictionary right away.

--HG--
extra : convert_revision : d6f6f5cc454a479e27718ec7952cd7559229ebe7
2005-03-22 00:53:01 -05:00
Nathan Binkert
eebe4e7fcc Sort the sim objects in the python output
python/m5/config.py:
    Turn back on the sorting of sim objects so we get consistent
    output.  This can lead to slight changes in stats.

--HG--
extra : convert_revision : 8ef9bd534cd2344acd69af7f52ee90b8b1afeb24
2005-03-22 00:08:54 -05:00
Steve Reinhardt
fc04f8015f Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/m5-head

--HG--
extra : convert_revision : a1cca61433e2cc9fd99d1a2361d32ea5c91b09c7
2005-03-19 08:47:19 -05:00
Steve Reinhardt
c929ee2c10 Byproducts of aborted attempt to refine 'parent' proxy semantics.
Mostly cleanup of mpy_importer.mpy_parse().

python/m5/__init__.py:
    Move panic() up to top in case we want to use it
    in mpy_importer (though I ended up not doing that
    after all).
python/m5/config.py:
    Add a couple of comments and a check for expressions
    like parent.any.foo (which is illegal).

--HG--
extra : convert_revision : dfc99ac9b1a2d91a736ca0b773b6d3c528a4f3cc
2005-03-18 13:34:28 -05:00
Lisa Hsu
3d51dc4132 Merge zizzer:/bk/m5 into zed.eecs.umich.edu:/z/hsul/work/m5/pact05
--HG--
extra : convert_revision : a0a10fccc03edcc5164536ea853788b982e332d7
2005-03-17 14:34:03 -05:00
Lisa Hsu
5977324255 allow the call to len on Value proxy.
--HG--
extra : convert_revision : 1a0aaf8db5ef60e0e7fc053bf4605eb90bb6e9e0
2005-03-17 14:31:08 -05:00
Steve Reinhardt
8b9e38c303 Merge zizzer.eecs.umich.edu:/z/stever/bk/m5-head
into zizzer.eecs.umich.edu:/z/stever/bk/m5-py

--HG--
extra : convert_revision : 39f30bd052c0f2b88524311d674bad7a0fae6358
2005-03-16 23:10:22 -05:00
Steve Reinhardt
0903013669 Allow proxies to refer to proxies in config files.
python/m5/config.py:
    Allow proxies to refer to other proxies and resolve by recurseivly calling unproxy().
    Not sure this works completely (since I don't have any examples to test it on)
    but it doesn't seem to break any existing config scripts.

--HG--
extra : convert_revision : d7fc272d0777d85f89104dfb5d1c5e4d8ddd6d6f
2005-03-16 23:10:17 -05:00
Nathan Binkert
ab5eb7d455 Make panic work in m5.config
python/m5/config.py:
    get panic from the m5 package.

--HG--
extra : convert_revision : 0965c13086f5eef7214298227c34cd9693534555
2005-03-16 20:32:37 -05:00
Steve Reinhardt
c8538d6a7e Enhancements to python config proxy class.
python/m5/config.py:
    - Enhanced Proxy class now supports subscripting, e.g.,
    parent.cpu[0] or even parent.cpu[0].icache.

    - Proxy also supports multiplication (e.g., parent.cycle * 3),
    though this feature has not been tested.

    - Subscript 0 works even on non-lists, so you can safely say
    cpu[0] and get the first cpu even if there's only one.

    - Changed name of proxy object from 'Super' to 'parent', and
    changed "wild card" notation from plain 'Super' to 'parent.any'.
python/m5/objects/AlphaConsole.mpy:
python/m5/objects/BaseCPU.mpy:
python/m5/objects/BaseSystem.mpy:
python/m5/objects/Device.mpy:
python/m5/objects/Ethernet.mpy:
python/m5/objects/Ide.mpy:
python/m5/objects/IntrControl.mpy:
python/m5/objects/Pci.mpy:
python/m5/objects/PhysicalMemory.mpy:
python/m5/objects/Platform.mpy:
python/m5/objects/SimConsole.mpy:
python/m5/objects/SimpleDisk.mpy:
python/m5/objects/Tsunami.mpy:
python/m5/objects/Uart.mpy:
    Change 'Super.foo' to 'parent.foo' (and 'Super' to 'parent.any').

--HG--
extra : convert_revision : f996d0a3366d5e3e60ae5973691148c3d7cd497d
2005-03-16 00:40:48 -05:00
Steve Reinhardt
42753edb3c Add a comment to smartdict.py.
python/m5/smartdict.py:
    Add a comment explaining why this actually works.

--HG--
extra : convert_revision : 39cbde547f4bf6cf626ab1c0b6ef56a5788b09b8
2005-03-15 19:41:51 -05:00
Nathan Binkert
c2014cb5ad get rid of issequence and just use the isinstance builtin
--HG--
extra : convert_revision : eca99aa35ad5c5c1c86325f55cf693ff585c9826
2005-03-15 13:22:47 -05:00