Commit graph

2446 commits

Author SHA1 Message Date
Ali Saidi
00d58aeb4d forgot a negative sign
--HG--
extra : convert_revision : 9cdb00198979fca831d3e6840f9c534671ccead3
2006-02-19 00:28:53 -05:00
Ali Saidi
53d2c9398e Move Linux/Tru64 architecture independent code into kern/*
leaving dependent code making way  for solaris linux syscall emu.

SConscript:
    Add two new files for syscall emulation
    Add getDesc() function
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    move architecture independent code into kern/linux/linux.(hh|cc)
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.hh:
    Add getDesc function
kern/linux/linux.hh:
    move generi linux syscall emulation code into kern/linux
kern/tru64/tru64.hh:
    move generi tru64 syscall emulation code into kern/tru64
sim/process.cc:
sim/process.hh:
    Push the function determination and calling stuff down to LiveProcess
    and out of the Linux/Tru64 classes respectively
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    fnctl implementation was identical in tru64 and linux so moved to generic

--HG--
extra : convert_revision : 103293dbe6fe2f7892de4929d17dc085def77026
2006-02-18 23:44:22 -05:00
Korey Sewell
a48c24b61e Support NNPC and branch instructions ... Outputs to decoder.cc correctly
Edits to the CPU model may still need to be made to handle branch likely insts...

arch/isa_parser.py:
    add a NNPC operand ...
arch/mips/isa/base.isa:
    change SPARC to MIPS
arch/mips/isa/decoder.isa:
    typo < to >=
arch/mips/isa/formats/basic.isa:
    spacing
arch/mips/isa/formats/branch.isa:
    add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
    support for NNPC and R31
arch/mips/isa_traits.hh:
    NNPC Addr variable

--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
2006-02-18 23:17:45 -05:00
Gabe Black
bf4fb61fa1 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : 8b2759d670a6a60142be748817ccef736d61dabf
2006-02-18 20:58:26 -05:00
Gabe Black
db40f25616 Changed the isa from a class to a namespace, untemplated StaticInst and StaticInstPtr, converted things to using TheISA, cleaned up some header file paths, and improved the system which pulls header files from the appropriate architecture.
--HG--
extra : convert_revision : 5087333fbaf442efb4b55e70376244629fff507d
2006-02-18 20:58:08 -05:00
Lisa Hsu
a611b81003 few changes for nate:
1) cosmetic - removing visibility of meta axes except for the tick labels.
2) unless subticklabels defined, don't do meta axes. (instead of assuming if you have 3D graph, do meta axes)

--HG--
extra : convert_revision : 396011ffaa51ea4066b34257f6fd5b3faac9d242
2006-02-18 20:10:42 -05:00
Lisa Hsu
6cf0ba8495 remove print statements
--HG--
extra : convert_revision : abd635034424eeb9685aea777440a02887ce81a6
2006-02-18 18:39:19 -05:00
Lisa Hsu
71bf22165a more changes for subtick labels.
util/stats/barchart.py:
    oop forgot this for 1D graph cases.
util/stats/chart.py:
    need to add default param to chart.

--HG--
extra : convert_revision : f4e6c6c614d584e7928ed905e97608716455ab6c
2006-02-18 17:29:43 -05:00
Lisa Hsu
b00468ce8b Merge zizzer:/bk/m5
into  zed.eecs.umich.edu:/z/hsul/work/m5/clean

--HG--
extra : convert_revision : 5f7c75eb3f82d9b04edc0efece3b054b5d0fe81f
2006-02-18 17:24:37 -05:00
Lisa Hsu
ef14fd4ad3 Now you can have sublabels for every bar using the self.xsubticklabels parameter.
--HG--
extra : convert_revision : a6bdf3a972e81c84947b7d6ae76f828494a125c8
2006-02-18 17:24:23 -05:00
Korey Sewell
bd17580928 changes from mergedmem
arch/mips/isa/formats/branch.isa:
    add branch_likely member functions
cpu/base.hh:
cpu/exec_context.hh:
cpu/static_inst.hh:
    change from mergedmem

--HG--
extra : convert_revision : d6ad6943e2ef09eac91a466fc5c9bd8e66bf319a
2006-02-18 14:38:23 -05:00
Korey Sewell
159e334531 use string name to figure out if we have a "AndLink" instruction
arch/mips/isa/operands.isa:
    uq -> uw

--HG--
extra : convert_revision : eeac6dba813de8174d080a5fa9b5a396b345113a
2006-02-18 04:17:11 -05:00
Korey Sewell
6bf71f96f3 MIPS generates ISA code through scons '.../decoder.cc'!!!
Now, must create g++ compilable code ...

arch/mips/isa/decoder.isa:
    missing a '}' ... edited a few instruction decodings ...
arch/mips/isa/formats.isa:
    rearranged #include
arch/mips/isa/formats/branch.isa:
    add Branch Likely  and Unconditional format
arch/mips/isa/formats/int.isa:
    move OperateNopCheckDecode template to another file ...
arch/mips/isa/formats/noop.isa:
    change Alpha to Mips in noop.isa

--HG--
extra : convert_revision : 4bf955fa6dffbbc99fb95fee7878f691e3df5424
2006-02-18 03:12:04 -05:00
Kevin Lim
dd11b2c4ff Get rid of deque (poor memory allocation), switch them over to lists.
Beware that using size() on a list is a O(n) operation.

dev/ns_gige.hh:
    Remove typedefs that (I assume) were copied over from etherdev.hh.  They were unused in the ns_gige code.

--HG--
extra : convert_revision : 577954ec26b899bd6329ce6a4aaa1d9b0ba4f34c
2006-02-17 15:07:48 -05:00
Kevin Lim
d6a330ebb9 Remove fake fault.
Switch fault pointers to const pointers to prevent them from accidentally being changed.
Fix some coding style.

arch/alpha/ev5.cc:
cpu/o3/commit_impl.hh:
kern/kernel_stats.hh:
    Remove fake fault.
arch/alpha/faults.cc:
    Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally.
arch/alpha/faults.hh:
    Fix to have normal m5 line length limit, change pointers to const pointers.
sim/faults.cc:
sim/faults.hh:
    Remove fake fault, change pointers to const pointers.

--HG--
extra : convert_revision : 01d4600e0d4bdc1d177b32edebc78f86a1bbfe2e
2006-02-16 14:55:15 -05:00
Kevin Lim
c7624c26e7 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-new

arch/alpha/isa/mem.isa:
    Hand merge.

--HG--
extra : convert_revision : c557aa4c867d84ab01139e509ee9f2ed05dd8ea0
2006-02-16 12:03:44 -05:00
Kevin Lim
485568efa9 Fixes to handle generating the initiateAcc and completeAcc functions a little more cleanly.
arch/alpha/isa/mem.isa:
    Avoid explicitly declaring the Mem variable.  Instead break up the code blocks used to generate the initiate and complete functions.  The templates reflect which operands need to be declared for each function (src, dest, or both).

    Loads use both the EA code and mem acc code for the initiate, and memacc code and postacc code for the complete.
    Stores use both the EA code and mem acc code for the initiate, and only post acc code for the complete.
arch/isa_parser.py:
    Remove hack for mem ops.

--HG--
extra : convert_revision : a367797a2cb698762bfc27be1da00bcbe9367150
2006-02-16 11:55:28 -05:00
Korey Sewell
7446238118 Get ISA parser to at least include all the ISA correctly ... crashes with "None" error
arch/mips/isa/decoder.isa:
    CondBranch format split up into Branch & BranchLikely formats
arch/mips/isa/formats.isa:
    include util.isa
arch/mips/isa/formats/branch.isa:
    erroneous 'e' at top of code
arch/mips/isa/formats/util.isa:
    util.isa

--HG--
extra : convert_revision : 4fc44a05e2838749e66cd70f210e8a718b34cbf3
2006-02-16 02:51:04 -05:00
Korey Sewell
e7d16b0aef Merge zizzer:/bk/multiarch
into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch

--HG--
extra : convert_revision : 17b164847aee7e21d15d1a9d99aae43f46906c28
2006-02-16 02:40:04 -05:00
Korey Sewell
7c9ea671af file name changes ... minor ISA changes
arch/mips/isa/base.isa:
    restoring base.isa file ...
arch/mips/isa/formats/basic.isa:
    add c++ emacs header
arch/mips/isa/formats/branch.isa:
    added branch likely format
arch/mips/isa/formats/int.isa:
    small change to python code

--HG--
extra : convert_revision : defd592abb1a724f5f88b19c197b858420e92d17
2006-02-16 02:39:46 -05:00
Gabe Black
00f451cc02 Some changes which weren't needed before doing a bk pull were needed afterwards, for some reason.
arch/alpha/ev5.cc:
    Took out the unnecessary check for a null Fault pointer.
arch/alpha/isa/mem.isa:
    Changed Fault to Fault *, and removed underscores from fault names.

--HG--
extra : convert_revision : 367a58a375f911185ddcc5fc826034af96427461
2006-02-16 02:08:13 -05:00
Gabe Black
b161d2a731 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : d8626acb2686e123ad0bb6cf94e85c992657470d
2006-02-16 01:25:48 -05:00
Gabe Black
10c79efe55 Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA.
SConscript:
    The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
    Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
    Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
    Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
    Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
    Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
    Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
    Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
    Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
    Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
    Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
    Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
    Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
    Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
    Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
    Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
    Changed Fault to Fault *
dev/ns_gige.cc:
    Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
    Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
    Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
    Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
    Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
    This allocates the system wide faults.
sim/faults.hh:
    This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Removed the underscores from fault names.

--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
2006-02-16 01:22:51 -05:00
Gabe Black
7f17f1f2df Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

--HG--
extra : convert_revision : b4bbf63ec3b1c6de0ea7220e6dda5366c0529c07
2006-02-15 23:24:35 -05:00
Ron Dreslinski
d142788172 More compilation fixes.
Should we add a proxy_port that does the v->p address translation?
Should the proxy port return a fault on translation errors, if we add one?

arch/alpha/alpha_linux_process.cc:
    Syscalls use a memPort through the CPU now instead of a xc functional memory.
cpu/base.hh:
    Add a pointer to the memPort syscalls will use.  Should this be a proxy_port that does address translation?
cpu/exec_context.cc:
cpu/exec_context.hh:
    Remove functional memory from the exec context
cpu/simple/cpu.cc:
    Set the memPort to be used as the syscall port as the dcache port
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Syscalls use a memPort through the CPU now instead of a xc functional memory.
    Also, fix the fact that readStringFunctional doesn't return a fault... should proxy_port handle this because it is doing the translation?

--HG--
extra : convert_revision : 1f65318c6594301a75dc4dc0c99fdd436b094a7f
2006-02-15 22:05:23 -05:00
Steve Reinhardt
b8a2d1e5c7 More progress toward compiling... partly by
fixing things, partly by ignoring CPU models
that don't currently compile.

SConscript:
    Split sources for fast, simple, and o3 CPU models into
    separate source lists.  For now none of these are included
    in the base source list, so you won't get any CPU models
    at all... but we still can't compile the other stuff so
    it's not an issue.

    Also get rid of obsolete encumbered/mem file.
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
cpu/exec_context.cc:
sim/process.cc:
sim/system.cc:
sim/system.hh:
    FunctionalMemory -> Memory
cpu/pc_event.hh:
    Get rid of unused badpc.
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Move Port functions into .cc file.
mem/port.hh:
    Make recvAddressRangesQuery panic by default instead
    of being abstract... do CPUs need to implement this?
mem/request.hh:
    Add prefetch flags.
sim/syscall_emul.hh:
    Start to fix...

--HG--
extra : convert_revision : ece53b3855f20916caaa381598ac37e8c7adfba7
2006-02-15 17:52:49 -05:00
Kevin Lim
091e6b72cf Slightly fix compiling. Now decoder.cc fails on trying to set some flags that no longer exist (PF_EXCLUSIVE, EVICT_NEXT).
--HG--
extra : convert_revision : f7fb9c73034e3ce647681c1097ae0f627f96c0dc
2006-02-15 16:40:02 -05:00
Ron Dreslinski
90def9ea9e Changes to start making the tree use the new memory system. Trying to compile decoder.cc but fails still.
SConscript:
    Place the memory objects back in the right place
arch/alpha/isa_desc:
    Fix includes to point to the new memory requests
cpu/exec_context.hh:
    Exec context now points to memory object, fix the include paths.
    Convert to prot_read/prot_write functions instead of read and write.
    Convert to new CpuRequestPtr instead of MemReqPtr.
mem/request.hh:
    Add back in support for Request Flags (needed by decoder to tag request) Removed the flags that were associated with packets/coherence.
sim/process.hh:
    Converted to point to new memory objects

--HG--
extra : convert_revision : a0b95380915d63b53194e2a26336d6adb1a0086b
2006-02-15 14:53:02 -05:00
Ron Dreslinski
7f114ca419 Many changes that make the new mem system compile. Now to convert the rest of the tree to use the new mem system.
mem/mem_object.hh:
    Create constrtor so it compiles
mem/packet.hh:
    Fix typedefs so they compile, add in a few more headers for compilation
mem/page_table.cc:
    convert to new mem system so it compiles
mem/page_table.hh:
    fix it to the version that had asid support.  Make it compile in the new system
mem/physical.cc:
    Fix some compilation bugs
mem/physical.hh:
    Add a type that made compile fail
mem/port.hh:
    Fix a spelling error that messed up compilation
mem/request.hh:
    fix typedefs and forward declerations so it compiles

--HG--
extra : convert_revision : 580fb1ba31ada799ff0122601b8b5a8d994bb8af
2006-02-15 14:21:09 -05:00
Korey Sewell
a0cdf213ab ...
arch/mips/isa/base.isa:
    restore base.isa

--HG--
extra : convert_revision : a551caae28f505b22bceae3297fc00b0fb6a0e23
2006-02-15 14:08:54 -05:00
Kevin Lim
2d04f18674 Gives separate methods for initiating and completing a memory access, which will be helpful for the merged memory model.
arch/alpha/isa/mem.isa:
    Include methods that allow a memory operation to be split between the part that initiates the access, and the part that completes the access.  In these functions the Mem variable is explicitly declared; in the default execute functions, the Mem variable is still handled through %(op_decl)s.
arch/isa_parser.py:
    Include recording the type of the memory access variable so that it can be used if it needs to be explicitly declared in a template.

    Have memory operands consider themselves neither a source nor a destination to avoid including themselves on the op_src_decl list or the op_dest_decl list.

    Record op_src_decl and op_dest_decl lists to allow for declaring only source or destination operands.  This is needed for the split memory access methods.

--HG--
extra : convert_revision : f674f7a2f747ae40ba8c3a0933b0337c87ee0b6c
2006-02-15 13:05:21 -05:00
Ali Saidi
7b42d61f13 Merge zizzer:/bk/m5
into  pb15.local:/Users/ali/work/m5.head

sim/byteswap.hh:
    SCCS merged

--HG--
extra : convert_revision : 65989fef265ddfafb59a6c96e3cdde76eb3e071d
2006-02-15 01:27:06 -05:00
Ali Saidi
18a0fa3e0c endian fixes and compiles on mac os x
arch/alpha/alpha_linux_process.cc:
    add endian conversions for fstat functions
arch/alpha/alpha_tru64_process.cc:
    add endian conversions for various functions
sim/byteswap.hh:
    for some reason gcc on macos really wants long and unsigned long
    Why int32_t and uint32_t isn't sufficient I don't know.
sim/process.cc:
sim/syscall_emul.hh:
    endian fixes

--HG--
extra : convert_revision : ce625d5660b70867c43c74fbed856149c0d8cd36
2006-02-15 01:23:13 -05:00
Korey Sewell
aee1bf5873 Merge zizzer:/bk/multiarch
into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch

--HG--
extra : convert_revision : 5b0a3dd1a52ca9b29ea4a1c505a7435bfd6110fe
2006-02-14 22:43:26 -05:00
Korey Sewell
23bbec6a34 another big step to a parsable ISA ... no errors after I used a symbolic link for
arch/alpha/main.isa to test my files ...

arch/mips/isa/operands.isa:
    use sd and ud instead of sdw and udw

--HG--
extra : convert_revision : d66f3fd2c4a4d70e6015f0f1643c400cdfe73055
2006-02-14 22:43:14 -05:00
Korey Sewell
5830200d78 trying to get ISA to parse correctly ...
arch/mips/isa/formats/unimp.isa:
    holds unimplemented formats
arch/mips/isa/formats/unknown.isa:
    holds unknown formats

--HG--
extra : convert_revision : 0f3a8ea7e3a1592322cce54527d6989152e57975
2006-02-14 21:26:01 -05:00
Gabe Black
7826fcd09d New files to fix building the SPARC_SE and MIPS_SE isa_parser.py generated files.
--HG--
extra : convert_revision : 94a9543376f8b4709a4aef54c5ac0d6f582a9dad
2006-02-14 20:13:08 -05:00
Gabe Black
085b73fe44 Fixed a path in the alpha isa description.
--HG--
extra : convert_revision : 2a73ef7703ffe5c5232619698a16c8b4ee265a21
2006-02-14 03:57:42 -05:00
Korey Sewell
9f584bcc6f Merge zizzer:/bk/multiarch
into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch

--HG--
extra : convert_revision : 62d9346c44d5b7d455414fbebf0da3a8ef8d0754
2006-02-14 02:12:39 -05:00
Korey Sewell
d7ac2b56c2 make MIPS MT instructions decodable ...
arch/mips/isa/bitfields.isa:
    extra bitfield for decoding

--HG--
extra : convert_revision : 27f0afc3ee6ce00a94f44b2b1ac160ec26030866
2006-02-14 02:03:14 -05:00
Gabe Black
19e5efed03 Pseudo instructions are now passed whatever instructions they need by the decoder, rather than extracting them explicitly. This lets most of the pseudo instruction code to be shared across architectures.
SConscript:
    Moved pseudo_inst.hh from targetarch to full system sources
arch/alpha/SConscript:
    Moved pseudo_inst.cc out of the alpha specific sources
arch/alpha/isa/decoder.isa:
    The decoder now pulls out the arguments for the pseudo instructions based on the alpha ABI
arch/alpha/isa/main.isa:
    Registers 16, 17 and 18 are used to get parameters for the pseudo instructions and can be referred to explicitly
sim/pseudo_inst.cc:
    Changed some include paths to reflect that pseudo_inst.hh is now outside of the alpha directory. Also, instead of extracting their parameters directly, they're passed in as regular function arguments.
sim/pseudo_inst.hh:
    Changed the function prototypes to include the functions parameters, now that they aren't extracted from the execution context.

--HG--
rename : arch/alpha/pseudo_inst.cc => sim/pseudo_inst.cc
rename : arch/alpha/pseudo_inst.hh => sim/pseudo_inst.hh
extra : convert_revision : 76ce768cf1d8a838aa7b64878a7ab4c4215ac999
2006-02-12 17:38:10 -05:00
Gabe Black
2c5e03550a Removed isa_traits.hh from targetarch, moved vptr.hh from arch/alpha to sim, fixed an include to have the new location, and removed an ambiguating function declaration in byteswap.hh.
SConscript:
    Moved isa_fullsys_traits.hh out of targetarch, since the only place it's included, and the only place the comments in the file say it should be included, is in the alpha isa_traits.hh
    targetarch/isa_traits.hh is now included through arch/isa_traits.hh
    vptr.hh was removed from targetarch, and moved to sim
arch/alpha/pseudo_inst.cc:
    Moved vptr.hh from targetarch to sim
base/loader/object_file.hh:
base/loader/symtab.hh:
cpu/base.hh:
dev/ide_disk.cc:
    Changed the include of isa_traits.hh from targetarch to arch
cpu/static_inst.hh:
dev/platform.hh:
dev/simple_disk.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/mbuf.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/process.hh:
sim/syscall_emul.hh:
    Changed the include of isa_traits.hh from targetarch to arch.
kern/linux/linux_threadinfo.hh:
    Changed the include of vptr.hh from targetarch to sim.
sim/byteswap.hh:
    Removed the line declaring swap_byte(long), since it ambiguates with swap_byte(int32_t)
sim/vptr.hh:
    Fixed the assert in the equals operator.
    Changed the AlphaISA namespace reference to TheISA.
    Changed arch/alpha/vtophys.hh to targetarch/vtophys.hh, since this file is now for all architectures.
    Added an include of arch/isa_traits.hh so that TheISA would be defined.

--HG--
extra : convert_revision : e3c6ac17ed0277cfeba1d35cd63eba66eba5996f
2006-02-12 12:40:58 -05:00
Gabe Black
4d4c105ac5 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : baf9b0eb84df7da8152ddf9a25264e041a24b8ca
2006-02-12 12:17:51 -05:00
Gabe Black
47a065d9f0 vptr.hh:
Rename: arch/alpha/vptr.hh -> sim/vptr.hh

--HG--
rename : arch/alpha/vptr.hh => sim/vptr.hh
extra : convert_revision : 345745efec49f6169d1d9f61fd590240a995373b
2006-02-12 12:14:14 -05:00
Gabe Black
94590a4dba Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

--HG--
extra : convert_revision : 427b5c957f91e66271444acebc01e1a861790363
2006-02-12 11:38:26 -05:00
Steve Reinhardt
79613686f0 Polishing of isa_parser.py internal operand handling, resulting in
minor change to syntax of 'def operands' in ISA descriptions.

arch/alpha/isa/main.isa:
arch/mips/isa/operands.isa:
arch/sparc/isa/operands.isa:
    Change 'def operands' statement to work with new
    isa_parser changes.
arch/isa_parser.py:
    Merge OperandTraits and OperandDescriptor objects into a
    unified hierarchy of Operand objects.
    Required a change in the syntax of the 'def operands'
    statement in the ISA description.

--HG--
extra : convert_revision : cb43f1607311497ead88ba13953d410ab5bc6a37
2006-02-12 00:31:19 -05:00
Steve Reinhardt
8f2e096275 Minor cleanup of operand type and traits code in isa_parser.py.
arch/isa_parser.py:
    Minor cleanup of operand type and traits code:
    - build operand size map right away when types are defined
    instead of waiting to do it lazily
    - check that operand types have been defined before operands
    - don't use 'type' as a variable name
    - use isinstance() instead of checking for types directly

--HG--
extra : convert_revision : 099c1ee8d490f9c38316749bf87209388c55c971
2006-02-11 21:26:49 -05:00
Steve Reinhardt
3cc6c59582 Add keyword parameters and list-valued arguments to
instruction format functions in ISA description language.

Take advantage of these features to clean up memory
instruction definitions in Alpha.

arch/alpha/isa/decoder.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
    Take advantage of new keyword parameters to disambiguate
    instruction vs. memory-request flags, and to provide
    a default EA calculation for memory ops (since 99% of them
    are the same).
arch/isa_parser.py:
    Add two new features to instruction format functions:
    - Keyword parameters, a la Python.
    - List-valued arguments.

    Also export makeList() function to Python code blocks,
    as this is handy for dealing with flags.

--HG--
extra : convert_revision : 99bbbaa2e765230aa96b6a06ed193793325f9fb0
2006-02-11 15:11:00 -05:00
Ali Saidi
59ba3d463c fix #if. I wonder why my compiler had no issues. Even though it is clearly
wrong

arch/alpha/alpha_linux_process.cc:
    fix #if. I wonder why my compiler had no issues

--HG--
extra : convert_revision : 880a0442b28811db5ec548ce940060d4b26ec634
2006-02-11 11:01:51 -05:00
Ali Saidi
96d6ac441c hello world works on a BE host for a LE guest
arch/alpha/alpha_linux_process.cc:
    Add endian conversions to fstat
sim/byteswap.hh:
    for some reason I don't understand g++ really wanted a long version defined
    even though int32_t should be the same.

--HG--
extra : convert_revision : 5bfe9d3f0b31824fa5a7ae3f51fd0be5ed4d555d
2006-02-11 00:55:36 -05:00