Commit graph

273 commits

Author SHA1 Message Date
Steve Reinhardt
997fc505a8 Make memory commands dense again to avoid cache stat table explosion.
Created MemCmd class to wrap enum and provide handy methods to
check attributes, convert to string/int, etc.

--HG--
extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b
2007-02-07 10:53:37 -08:00
Ali Saidi
ebb6972dd3 more fp fixes
fix unaligned accesses in mmaped disk device

src/arch/sparc/isa/decoder.isa:
    get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code
src/arch/sparc/isa/formats/basic.isa:
    move the cexec into the aexec field
src/cpu/exetrace.cc:
    copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer
src/dev/sparc/mm_disk.cc:
src/dev/sparc/mm_disk.hh:
    fix unaligned accesses in the memory mapped disk device

--HG--
extra : convert_revision : aaa33096b08cf0563fe291d984a87493a117e528
2007-02-06 15:52:33 -05:00
Ali Saidi
fc79ace502 Make SPARC checkpointing work
src/arch/sparc/floatregfile.cc:
    Fix serialization for fpreg
src/arch/sparc/intregfile.cc:
    fix serialization for intreg
src/arch/sparc/miscregfile.cc:
    fix serialization from miscreg
src/arch/sparc/pagetable.cc:
    fix serialization for page table
src/arch/sparc/regfile.cc:
    need to serialize nnpc
src/arch/sparc/tlb.cc:
    write serialization code for tlb
src/cpu/base.cc:
    provide a way to find the thread number a context is
    serialize the instruction counter
src/cpu/base.hh:
    provide a way to find the thread number a context is
    and given a thread number find a context pointer
src/cpu/cpuevent.hh:
    provide method to get thread context from a cpu event for serialization
src/dev/sparc/t1000.cc:
src/dev/sparc/t1000.hh:
    nothing to serialize in t1000
src/sim/serialize.cc:
src/sim/serialize.hh:
    Make findObj() work (it hasn't since we did the python conversion stuff)

--HG--
extra : convert_revision : a95bc4e3c3354304171efbe3797556fdb146bea2
2007-01-30 18:25:39 -05:00
Ali Saidi
d92f0d370b timegm() is a gnuism... replace with the code from the timegm() man page
--HG--
extra : convert_revision : f2b80a0b7768edc370e3f07c45cb3bb9a46450a9
2007-01-29 19:04:06 -05:00
Nathan Binkert
37795b104d Stick the conversion of python to unix time with all of
the other param code so that other functions can use it
as well.

--HG--
extra : convert_revision : a8becdeadc70af0b64bff5b0770788dfba6e1857
2007-01-28 10:26:59 -08:00
Ali Saidi
6d9d0c68b5 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.suncc

--HG--
extra : convert_revision : 1706f6218abec7eb575dcff3ad4aef83894f64ab
2007-01-26 18:50:28 -05:00
Ali Saidi
fd8a4ff5a8 Merge zeep.pool:/z/saidi/work/m5.newmem
into  zeep.pool:/z/saidi/work/m5.suncc

--HG--
extra : convert_revision : 20f61a524a3b53fc0afcf53a24b5a1fe1d96f579
2007-01-26 18:49:40 -05:00
Ali Saidi
63fdabf191 make our code a little more standards compliant
pretty close to compiling w/ suns compiler

briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops

SConstruct:
    Add code to detect compiler and choose cflags based on detected compiler
    Fix zlib check to work with suncc
src/SConscript:
    split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
    use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
    add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
    use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
    include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
    remove dangling comma
src/arch/sparc/system.cc:
    dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
    use std namespace for string ops
src/arch/sparc/utility.hh:
    no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
    dummy returns to for suncc front end
src/base/cprintf.hh:
    use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
    don't need to define hash for suncc
src/base/hostinfo.cc:
    need stdio.h for sprintf
src/base/loader/object_file.cc:
    munmap is in std namespace not null
src/base/misc.hh:
    use M5 generic noreturn macros
    use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
    we need file.h for file flags
src/base/random.cc:
    mess with include files to make suncc happy
src/base/remote_gdb.cc:
    malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
    use std namespace for floor
src/base/stats/text.cc:
    include math.h for rint (cmath won't work)
src/base/time.cc:
    use suncc version of ctime_r
src/base/time.hh:
    change macro to work with both gcc and suncc
src/base/timebuf.hh:
    include cstring from memset and use std::
src/base/trace.hh:
    change variadic macros to be normal format
src/cpu/SConscript:
    add dummy returns where appropriate
src/cpu/activity.cc:
    include cstring for memset
src/cpu/exetrace.hh:
    include cstring fro memcpy
src/cpu/simple/base.hh:
    add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
    add dummy return where appropriate
src/dev/ide_atareg.h:
    make define work for both gnuc and suncc
src/dev/io_device.hh:
    add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
    include cstring for string ops
src/dev/sparc/mm_disk.cc:
    add dummy return where appropriate
    include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
    Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
    cast hastSets to double for log() call
src/mem/physical.cc:
    cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
    make define work for suncc and gnuc

--HG--
extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
2007-01-26 18:48:51 -05:00
Nathan Binkert
73dd0ea357 Instead of passing an int to represent time between python and C++
pass the tuple of python's struct_time and interpret that.
Fixes a problem where the local timezone leaked into the time
calculation.  Also fix things so that the unix, python, and RTC
data sheets all get the right time.  Provide both years since 1900
and BCD two digit year.
Put the date back at 1/1/2006 for now.

--HG--
extra : convert_revision : 473244572f468de2cb579a3dd7ae296a6f81f5d7
2007-01-25 14:59:41 -05:00
Ali Saidi
3af3610c62 add dumb time of day device
--HG--
extra : convert_revision : 52e51ff49f7ed73065f04707ded06dc7254292c4
2007-01-21 18:04:40 -05:00
Ali Saidi
7933aade85 add memory mapped disk device
configs/common/FSConfig.py:
src/python/m5/objects/T1000.py:
    add configuration for memory mapped disk
src/dev/sparc/SConscript:
    add memory mapped disk to sconscript

--HG--
extra : convert_revision : d8df4a455cf48000042d0ff93a274985f4dbe905
2007-01-09 22:16:49 -05:00
Nathan Binkert
fc45d42d01 Add 'Time' as a parameter type that can accept various
formats for time (strings, datetime objects, etc.)
Advance system time to 1/1/2009
Clean up time management code a little bit

--HG--
extra : convert_revision : 28ebecc7ea6b12f4345c77a9a6b4bdf2e752c4f8
2007-01-03 10:12:55 -08:00
Nathan Binkert
2d029fe584 Make sure that all of the bits in the result are set
to some value.

--HG--
extra : convert_revision : 1f1700fd77531cbb8cfad7f04ce2b573fcdefdab
2006-12-24 15:15:12 -08:00
Lisa Hsu
551ba56ae2 little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).
RangeSize as a function takes a start address, and a SIZE, and will make the range (start, start+size-1) for you.

src/cpu/memtest/memtest.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/lsq.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.hh:
    Fix RangeSize arguments
src/dev/alpha/tsunami_cchip.cc:
src/dev/alpha/tsunami_io.cc:
src/dev/alpha/tsunami_pchip.cc:
src/dev/baddev.cc:
    pioSize indicates SIZE, not a mask

--HG--
extra : convert_revision : d385521fcfe58f8dffc8622260937e668a47a948
2006-12-15 17:55:47 -05:00
Ali Saidi
139519ef87 Fix bugs in tlbmap (and thus rangemap since the code is nearly identical)
Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing)
Fix tcc instruction igoner in legion-lock stuff to be correct in all cases
Have console interrupts warn rather than panicing until we figure out what to do with interrupts

src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
    add a magic miscreg which reads all the bits the tlb needs in one go
src/arch/sparc/tlb.cc:
    initialized the context type and id to reasonable values and handle block init stores
src/arch/sparc/tlb_map.hh:
    fix bug in tlb map code
src/base/range_map.hh:
    fix bug in rangemap code and add range_multimap
    (these are probably useful for bus range stuff)
src/cpu/exetrace.cc:
    fixup tcc ignore code to be correct
src/dev/sparc/t1000.cc:
    make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out
src/unittest/rangemaptest.cc:
    fix up the rangemap unit test to catch the missing case

--HG--
extra : convert_revision : 70604a8b5d0553aa0b0bd7649f775a0cfa8267a5
2006-12-12 17:55:27 -05:00
Ali Saidi
92c5a5c8cb More changes to get SPARC fs closer. Now at 1.2M cycles before difference
configs/common/FSConfig.py:
    seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
    change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
    For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
    Use instruction count from cpu rather than cycles because that is what legion does
    we can change it back after were done with legion
src/base/bitfield.hh:
    add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
    add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
    compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
    change asserts of packet success to if panics wrapped with NDEBUG defines
    so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
    expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
    convert some tabs to spaces
src/python/m5/objects/T1000.py:
    add more fake devices for each l1 bank and each memory controller

--HG--
extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276
2006-12-04 00:54:40 -05:00
Ali Saidi
8c4f7a0404 Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
Add the ability to use an address mask for symbol loading
Rather then silently failing on platform accesses panic
Move BadAddr/IsaFake no Device from Tsunami
Let the system kernel be none, but warn about it

configs/common/FSConfig.py:
    We don't have a kernel for sparc yet
src/arch/sparc/system.cc:
    Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
src/base/loader/aout_object.cc:
src/base/loader/aout_object.hh:
src/base/loader/ecoff_object.cc:
src/base/loader/ecoff_object.hh:
src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.hh:
src/base/loader/raw_object.cc:
src/base/loader/raw_object.hh:
    Add the ability to use an address mask for symbol loading
src/dev/sparc/t1000.cc:
    Rather then silently failing on platform accesses panic
src/dev/sparc/t1000.hh:
    fix up a couple of platform comments
src/python/m5/objects/Bus.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/T1000.py:
src/python/m5/objects/Tsunami.py:
    Move BadAddr/IsaFake no Device from Tsunami
src/python/m5/objects/System.py:
    Let kernel be none
src/sim/system.cc:
    Let the system kernel be none, but warn about it

--HG--
extra : convert_revision : 92f6afef599a3d3c7c5026d03434102c41c7b5f4
2006-11-30 15:51:54 -05:00
Gabe Black
bc4d15ddd1 Create a stub t1000 platform.
--HG--
extra : convert_revision : 7e27b23b66c743b4625a1dd9d8d6ba61bff45168
2006-11-14 15:14:27 -05:00
Ali Saidi
aa19b2e7bc fix endian issues with condition codes
use memcpy instead of bcopy
s/u_int32_t/uint32_t/g
fixup endian code to work with solaris
hack to make sure htole() works... Nate, have a good idea to fix this?

src/arch/sparc/faults.cc:
    set the reset address to be 40 bits. Makes PC printing easier at least for now.
src/arch/sparc/isa/base.isa:
    fix endian issues with condition codes
src/arch/sparc/tlb.hh:
    add implemented physical addres constants
src/arch/sparc/utility.hh:
    add tlb.hh to utilities
src/base/loader/raw_object.cc:
    add a symbol <filename>_start to the symbol table for binaries files
src/base/remote_gdb.cc:
    use memcpy instead of bcopy
src/cpu/exetrace.cc:
    clean up printing a bit more
src/cpu/m5legion_interface.h:
    add tons to the shared interface
src/dev/ethertap.cc:
    s/u_int32_t/uint32_t/g
src/dev/ide_atareg.h:
    fixup endian code to work with solaris
src/dev/pcidev.cc:
src/sim/param.hh:
    hack to make sure htole() works...

--HG--
extra : convert_revision : 4579392184b40bcc1062671a953c6595c685e9b2
2006-11-10 20:17:42 -05:00
Gabe Black
f720029e97 Merge zizzer.eecs.umich.edu:/bk/newmem/
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : dc165840841bdd88e40111b98d1be493441703f0
2006-11-08 16:18:10 -05:00
Kevin Lim
244e0c884c Remove hack by setting configuration better.
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
    No need for specialized init() function any more.
src/python/m5/objects/Tsunami.py:
    Override responder when set by user.  This avoids having bus.responder floating around and not doing anything when the user has specified their own default responder.

--HG--
extra : convert_revision : c547daf15b23a889c98e62bfd53c293c85d7a041
2006-11-07 14:24:31 -05:00
Gabe Black
5411fbe6e8 Removed unnecessary arch/alpha/ev5.hh include
--HG--
extra : convert_revision : e8277cc279be839c1754b5da96f9153da06d3ec1
2006-11-07 05:42:52 -05:00
Gabe Black
b156767f1e Get rid of pcifake.cc and tsunami_fake.cc to go with the merged default devices.
--HG--
extra : convert_revision : e88aaaa43843c1283f29cef0886e057412705899
2006-11-06 19:56:57 -05:00
Gabe Black
02abca6b9e Merge zizzer.eecs.umich.edu:/bk/newmem/
into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

src/SConscript:
    SCCS merged

--HG--
extra : convert_revision : f130c8a2d33f58d857e5d5a02bb9698c1bceb23b
2006-11-06 19:52:32 -05:00
Gabe Black
dd14c86ec8 Moved the tsunami devices into the dev/alpha directory. Other devices "generic" devices are dependent on some of those files. That will either need to change, or most likely those devices will have to be considered architecture dependent.
--HG--
rename : src/dev/tsunami.cc => src/dev/alpha/tsunami.cc
rename : src/dev/tsunami.hh => src/dev/alpha/tsunami.hh
rename : src/dev/tsunami_cchip.cc => src/dev/alpha/tsunami_cchip.cc
rename : src/dev/tsunami_cchip.hh => src/dev/alpha/tsunami_cchip.hh
rename : src/dev/tsunami_io.cc => src/dev/alpha/tsunami_io.cc
rename : src/dev/tsunami_io.hh => src/dev/alpha/tsunami_io.hh
rename : src/dev/tsunami_pchip.cc => src/dev/alpha/tsunami_pchip.cc
rename : src/dev/tsunami_pchip.hh => src/dev/alpha/tsunami_pchip.hh
rename : src/dev/tsunamireg.h => src/dev/alpha/tsunamireg.h
extra : convert_revision : ffbb6fd93341d2623a6932bf096019b8976da694
2006-11-06 19:45:00 -05:00
Gabe Black
5b152b970b Got rid of stray alpha include
--HG--
extra : convert_revision : eddd64dd9291d6656821fe6387aeab2f9ddbaf58
2006-11-06 19:10:13 -05:00
Gabe Black
1ffff78ca9 Created seperate SConscript for the dev directory. Made subdirectories for Alpha and SPARC and put SConscripts in them.
--HG--
rename : src/base/kgdb.h => src/arch/alpha/kgdb.h
rename : src/dev/alpha_access.h => src/dev/alpha/access.h
rename : src/dev/alpha_console.cc => src/dev/alpha/console.cc
rename : src/dev/alpha_console.hh => src/dev/alpha/console.hh
extra : convert_revision : a7dd466308cb83edc40528689aacb72413089cdf
2006-11-06 18:26:11 -05:00
Ali Saidi
bf3223d7ce delete pcifake, tsunamifake. Combine BadAddr/IsaFake into one
src/SConscript:
    remove pcifake and tsunami fake from sconscript
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
    combine badaddr and isa fake into one
src/python/m5/objects/Pci.py:
    remove pcifake
src/python/m5/objects/Tsunami.py:
    make badaddr derive from isafake

--HG--
extra : convert_revision : 91470db60aa1de6b85827304e27bd3414cc9d8d1
2006-11-06 16:24:25 -05:00
Kevin Lim
c3485a6548 Implement device that will return BadAddress.
--HG--
extra : convert_revision : d833c20f691e01c84a0678f19f7d83f3ee50c0c1
2006-11-02 15:18:35 -05:00
Kevin Lim
5825a6c9d8 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix

configs/example/fs.py:
configs/example/se.py:
src/mem/tport.hh:
    Hand merge.

--HG--
extra : convert_revision : b9df95534d43b3b311f24ae24717371d03d615bf
2006-10-31 14:37:19 -05:00
Kevin Lim
b26355daa8 Ports now have a pointer to the MemObject that owns it (can be NULL).
src/cpu/simple/atomic.hh:
    Port now takes in the MemObject that owns it.
src/cpu/simple/timing.hh:
    Port now takes in MemObject that owns it.
src/dev/io_device.cc:
src/mem/bus.hh:
    Ports now take in the MemObject that owns it.
src/mem/cache/base_cache.cc:
    Ports now take in the MemObject that own it.
src/mem/port.hh:
src/mem/tport.hh:
    Ports now optionally take in the MemObject that owns it.

--HG--
extra : convert_revision : 890a72a871795987c2236c65937e06973412d349
2006-10-31 13:59:30 -05:00
Ali Saidi
baaadb0d43 add packet_access.hh
--HG--
extra : convert_revision : 7fe4958549101fca9613baa4a317d96f4970d432
2006-10-27 09:10:50 -04:00
Ali Saidi
0f98905ecc Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 4db140e6e8408b3ed39da327515b8e88a2701e6b
2006-10-24 12:59:19 -04:00
Nathan Binkert
dff1a022b8 Missing case
--HG--
extra : convert_revision : 128896dd1a654fe9a02e2c07ef6ce6799b62f21f
2006-10-21 00:31:46 -07:00
Ali Saidi
7be58fd5f4 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : c0f9bde20585b3811ff906728b003072b69696b5
2006-10-20 13:00:15 -04:00
Ali Saidi
32384b2f6b still working on getting past initialization
--HG--
extra : convert_revision : 7a5fccb9a19d363e479ef24012a7b8598272eaa9
2006-10-20 13:00:05 -04:00
Nathan Binkert
a4c6f0d69e Use PacketPtr everywhere
--HG--
extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
2006-10-20 00:10:12 -07:00
Nathan Binkert
7245d4530d refactor code for the packet, get rid of packet_impl.hh
and call it packet_access.hh and fix the #includes so
things compile right.

--HG--
extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
2006-10-19 23:38:45 -07:00
Ron Dreslinski
a17afb1649 Fix for DMA's in FS caches.
Fix CSHR's for flow control.
Fix for Bus Bridges reusing packets (clean flags up)

Now both timing/atomic caches with MOESI in UP fail at same point.

src/dev/io_device.hh:
    DMA's should send WriteInvalidates
src/mem/bridge.cc:
    Reusing packet, clean flags in the packet set by bus.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
    Fix CSHR's for flow control.
src/mem/packet.hh:
    Make a writeInvalidateResp, since the DMA expects responses to it's writes

--HG--
extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd
2006-10-13 15:47:05 -04:00
Lisa Hsu
97c1f6eff7 post checkpoint restoration the bus ranges need to be re-initialized for ALL pci devs, not just ide.
src/dev/ide_ctrl.cc:
    this range change needs to be done for all pio devices, not just the ide.
src/dev/pcidev.cc:
    range change needs to be done at here, not in the ide_ctrl file.

--HG--
extra : convert_revision : 60c65c55e965b02d671dba7aa8793e5a81f40348
2006-10-08 23:18:19 -04:00
Kevin Lim
4ed184eade Merge ktlim@zamp:./local/clean/o3-merge/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

configs/boot/micro_memlat.rcS:
configs/boot/micro_tlblat.rcS:
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa_traits.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/params.hh:
src/cpu/o3/checker_builder.cc:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/base.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.hh:
src/dev/ide_disk.cc:
src/python/m5/objects/O3CPU.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/System.py:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/system.hh:
util/m5/m5.c:
    Hand merge.

--HG--
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh
rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh
rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh
rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh
rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh
rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh
rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh
rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh
rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh
rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh
rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh
rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh
rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh
rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc
rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc
rename : cpu/thread_state.hh => src/cpu/thread_state.hh
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py
rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/system.hh => src/sim/system.hh
extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
2006-09-30 23:43:23 -04:00
Ali Saidi
17b0e9714d add boiler plate intel nic code
src/SConscript:
    add intel nic to sconscript
src/dev/pcidev.cc:
    fix bug with subsystemid value
src/python/m5/objects/Ethernet.py:
    add intel nic to ethernet.py
src/python/m5/objects/Ide.py:
src/python/m5/objects/Pci.py:
    Move config_latency into pci where it belogs

--HG--
extra : convert_revision : 7163aaf7b4098496518b0910cef62f2ce3dd574d
2006-09-18 20:12:45 -04:00
Steve Reinhardt
f9ae0dcf10 Move more common functionality into SimpleTimingPort,
allowing derived classes to be simplified.

--HG--
extra : convert_revision : c980d3aec5e6c044d8f41e96252726fe9a256605
2006-08-30 16:24:26 -07:00
Steve Reinhardt
a8a7ce2b88 Minor include file & formatting cleanup.
--HG--
extra : convert_revision : fa23563b2897687752379d63ddab5cccb92484ba
2006-08-30 09:57:46 -07:00
Steve Reinhardt
72eb4f5f12 Clean up BAR setting code.
--HG--
extra : convert_revision : 8378be6cd6f55af7a199296cb2ff61ee94849bf7
2006-08-28 11:17:49 -07:00
Steve Reinhardt
b77da23e1a Get rid of unneeded union.
Verify that BAR sizes are powers of two.

--HG--
extra : convert_revision : ce8dca07aaf1a340cc166b99b5858613a954e2fd
2006-08-28 11:01:25 -07:00
Steve Reinhardt
19d51452b1 Get rid of unused BARAddrs[] in PciConfigData object.
--HG--
extra : convert_revision : a82e05326ca6150c70cb288b28f9f6eee89ad93d
2006-08-28 10:34:15 -07:00
Steve Reinhardt
acfa88f732 Cleanup: formatting, comments, DPRINTFs.
--HG--
extra : convert_revision : 565ab099f1c0744a13959e721c19dd03b7630f04
2006-08-28 10:28:31 -07:00
Ali Saidi
ed58f77c47 fixes for gcc 4.1
Nate needs to fix sinic builder stuff
Gabe needs to verify my fixes to decoder.isa

OPT/DEBUG compiles for ALPHA_FS, ALPHA_SE, MIPS_SE, SPARC_SE with this changeset

README:
    Fix the swig version in the readme
src/SConscript:
    remove sinic until nate fixes the builder crap for it
src/arch/alpha/system.hh:
src/arch/mips/isa/includes.isa:
src/arch/sparc/isa/decoder.isa:
src/base/stats/visit.cc:
src/base/timebuf.hh:
src/dev/ide_disk.cc:
src/dev/sinic.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr_queue.cc:
src/mem/packet.hh:
src/mem/request.hh:
src/sim/builder.hh:
src/sim/system.hh:
    fixes for gcc 4.1

--HG--
extra : convert_revision : 3775427c0047b282574d4831dd602c96cac3ba17
2006-08-15 17:41:22 -04:00
Gabe Black
c9900f159e Fixed ALPHA_FS by moving the remnants of isa_fullsys_traits.hh into arch/alpha/pagetable.hh and fixing up some includes
--HG--
extra : convert_revision : 02a47fa62b17245763314890beb68339c789d18f
2006-08-15 04:46:51 -04:00
Steve Reinhardt
5bd07f98ed Fix up doxygen.
--HG--
rename : docs/footer.html => src/doxygen/footer.html
rename : docs/stl.hh => src/doxygen/stl.hh
extra : convert_revision : 2b2e5637930843c1be07deaa708fd4126213cda2
2006-08-14 19:25:07 -04:00
Kevin Lim
64b7213046 Need config read/write latency.
--HG--
extra : convert_revision : 2d978635db89e727f228890738b24fcad9b6ced6
2006-07-27 16:43:02 -04:00
Ali Saidi
851f91f245 Move PioPort timing code into Simple Timing Port object
Make PioPort use it
Make Physical memory use it as well

src/SConscript:
    Add timing port to sconscript
src/dev/io_device.cc:
src/dev/io_device.hh:
    Move simple timing pio port stuff into a simple timing port class so it can be used by the physical memory
src/mem/physical.cc:
src/mem/physical.hh:
    use a simple timing port stuff instead of rolling our own here

--HG--
extra : convert_revision : e5befbd295a572568cfdca533efb5ed1984c59d1
2006-07-20 19:03:47 -04:00
Ali Saidi
c368ff0bd8 add system.mem_mode = ['timing', 'atomic']
update scripts acordingly

configs/test/SysPaths.py:
    new syspaths from nate, this one allows you to set script, binary, and disk paths like
    system.dir = 'aouaou' in your script
configs/test/fs.py:
    update for system mem_mode
    Put small checkpoint example
    Make clock 1THz
configs/test/test.py:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/system.cc:
src/arch/alpha/tru64/system.cc:
src/arch/sparc/system.cc:
src/python/m5/objects/System.py:
src/sim/system.cc:
src/sim/system.hh:
    update for system mem_mode
src/dev/io_device.cc:
    Use time returned from sendAtomic to delay

--HG--
extra : convert_revision : 67eedb3c84ab2584613faf88a534e793926fc92f
2006-07-13 15:48:17 -04:00
Ali Saidi
2bc9229ea7 memory mode information now contained in system object
States are now running, draining, or drained. memory state information moved into system object
system parameter is not fs only for cpus
Implement drain() support in devices
Update for drain() call that returns number of times drain_event->process() will be called

Break O3 CPU! No sense in putting in a hack change that kevin is going to remove in a few minutes i imagine

src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
    Since se mode has a system, allow access to it
    Verify that the atomic cpu is connected to an atomic system on resume
src/cpu/simple/base.cc:
    Since se mode has a system, allow access to it
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Update for new drain() call that returns number of times drain_event->process() will be called and memory state being moved into the system
    Since se mode has a system, allow access to it
    Verify that the timing cpu is connected to an timing system on resume
src/dev/ide_disk.cc:
src/dev/io_device.cc:
src/dev/io_device.hh:
src/dev/ns_gige.cc:
src/dev/ns_gige.hh:
src/dev/pcidev.cc:
src/dev/pcidev.hh:
src/dev/sinic.cc:
src/dev/sinic.hh:
    Implement drain() support in devices
src/python/m5/config.py:
    Allow drain to return number of times drain_event->process() will be called. Normally 0 or 1 but things like O3 cpu or devices with multiple ports may want to call it many times
src/python/m5/objects/BaseCPU.py:
    move system parameter out of fs to everyone
src/sim/sim_object.cc:
src/sim/sim_object.hh:
    States are now running, draining, or drained. memory state information moved into system object
src/sim/system.cc:
src/sim/system.hh:
    memory mode information now contained in system object

--HG--
extra : convert_revision : 1389c77e66ee6d9710bf77b4306fb47e107b21cf
2006-07-12 20:22:07 -04:00
Kevin Lim
8bf9709d91 Two minor FS compile fixes.
src/dev/tsunami_pchip.hh:
    Need ULL() for 32-bit hosts.
src/sim/pseudo_inst.cc:
    Forgot to remove sampler include from here.

--HG--
extra : convert_revision : 6ab6bdc721290167b4c2b78da3d28a4992eb24d5
2006-07-06 16:26:44 -04:00
Ali Saidi
93839380e7 Add default responder to bus
Update configuration for new default responder on bus
Update to devices to handle their own pci config space without pciconfigall
Remove most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for
Remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same
bus:dev:func and interrupt
Remove pciconfigspace from pci devices, and py files
Add calcConfigAddr that returns address for config space based on bus/dev/function + offset

configs/test/fs.py:
    Update configuration for new default responder on bus
src/dev/ide_ctrl.cc:
src/dev/ide_ctrl.hh:
src/dev/ns_gige.cc:
src/dev/ns_gige.hh:
src/dev/pcidev.cc:
src/dev/pcidev.hh:
    Update to handle it's own pci config space without pciconfigall
src/dev/io_device.cc:
src/dev/io_device.hh:
    change naming for pio port
    break out recvTiming into two functions to reuse code
src/dev/pciconfigall.cc:
src/dev/pciconfigall.hh:
    removing most of pciconfigall, it now is a dumbdevice which gets it's address based on the bus it's supposed to respond for
src/dev/pcireg.h:
    add a max size for PCI config space (per PCI spec)
src/dev/platform.cc:
src/dev/platform.hh:
    remove need for pci config space from platform, add registerPciDevice function to prevent more than one device from having same
    bus:dev:func and interrupt
src/dev/sinic.cc:
    remove pciconfigspace as it's no longer a needed parameter
src/dev/tsunami.cc:
src/dev/tsunami.hh:
src/dev/tsunami_pchip.cc:
src/dev/tsunami_pchip.hh:
    add calcConfigAddr that returns address for config space based on bus/dev/function + offset (per PCI spec)
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
    add idea of default responder to bus
src/python/m5/objects/Pci.py:
    add config port for pci devices
    add latency, bus and size parameters for pci config all (min is 8MB, max is 256MB see pci spec)

--HG--
extra : convert_revision : 99db43b0a3a077f86611d6eaff6664a3885da7c9
2006-07-06 14:41:01 -04:00
Ali Saidi
69c34554e5 minor device fixups
configs/test/SysPaths.py:
    remove some tabs and add /n/poolfs/z/dist/m5/system
src/dev/io_device.cc:
    fix since pio timing dma packts colud be nacked too
src/dev/io_device.hh:
    move DmaReqState into DmaDevie

--HG--
extra : convert_revision : 2b5300d85ab33b3753afc54bc6a04a47b6e00d20
2006-06-18 11:10:08 -04:00
Nathan Binkert
e76a12834b Add myself to list of authors
--HG--
extra : convert_revision : 0c9a892127476d586fb8bff1b0eb7342c6b1f166
2006-06-17 17:49:38 -04:00
Steve Reinhardt
e981a97dec Move SimObject creation and Port connection loops
into Python.
Add Port and VectorPort objects and support for
specifying port connections via assignment.
The whole C++ ConfigNode hierarchy is gone now, as are
C++ Connector objects.

configs/test/fs.py:
configs/test/test.py:
    Rewrite for new port connector syntax.
src/SConscript:
    Remove unneeded files:
    - mem/connector.*
    - sim/config*
src/dev/io_device.hh:
src/mem/bridge.cc:
src/mem/bridge.hh:
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/mem_object.hh:
src/mem/physical.cc:
src/mem/physical.hh:
    Allow getPort() to take an optional index to
    support vector ports (eventually).
src/python/m5/__init__.py:
    Move SimObject construction and port connection
    operations into Python (with C++ calls).
src/python/m5/config.py:
    Move SimObject construction and port connection
    operations into Python (with C++ calls).
    Add support for declaring and connecting MemObject
    ports in Python.
src/python/m5/objects/Bus.py:
src/python/m5/objects/PhysicalMemory.py:
    Add port declaration.
src/sim/builder.cc:
src/sim/builder.hh:
src/sim/serialize.cc:
src/sim/serialize.hh:
    ConfigNodes are gone; builder just gets the
    name of a .ini file section now.
src/sim/main.cc:
    Move SimObject construction and port connection
    operations into Python (with C++ calls).
    Split remaining initialization operations into two parts,
    loadIniFile() and finalInit().
src/sim/param.cc:
src/sim/param.hh:
    SimObject resolution done globally in Python now
    (not via ConfigNode hierarchy).
src/sim/sim_object.cc:
    Remove unneeded #include.

--HG--
extra : convert_revision : 2fa4001eaaec0c9a4231ef6e854f8e156d930dfe
2006-06-13 23:19:28 -04:00
Ali Saidi
6875e8d839 add nacked result and a function to swizzle nacked packet into something that can be sent out again
implement ability for i/o devices to handle

src/dev/io_device.cc:
src/dev/io_device.hh:
    implement ability for i/o devices to handle
src/mem/packet.hh:
    add nacked result and a function to swizzle nacked packet into something that can be sent out again

--HG--
extra : convert_revision : fa42b01f4ab21562d37bd6bf6f4d7f69a94f0e86
2006-06-08 19:43:50 -04:00
Kevin Lim
eb0e416998 Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar.

src/arch/alpha/arguments.cc:
src/arch/alpha/arguments.hh:
src/arch/alpha/ev5.cc:
src/arch/alpha/faults.cc:
src/arch/alpha/faults.hh:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/freebsd/system.hh:
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/linux/system.hh:
src/arch/alpha/linux/threadinfo.hh:
src/arch/alpha/process.cc:
src/arch/alpha/regfile.hh:
src/arch/alpha/stacktrace.cc:
src/arch/alpha/stacktrace.hh:
src/arch/alpha/tlb.cc:
src/arch/alpha/tlb.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/system.cc:
src/arch/alpha/tru64/system.hh:
src/arch/alpha/utility.hh:
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/process.cc:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/regfile/regfile.hh:
src/arch/mips/stacktrace.hh:
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/regfile.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/stacktrace.hh:
src/arch/sparc/ua2005.cc:
src/arch/sparc/utility.hh:
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
src/base/remote_gdb.cc:
src/base/remote_gdb.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/exec_context.hh:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/cpuevent.cc:
src/cpu/cpuevent.hh:
src/cpu/exetrace.hh:
src/cpu/intr_control.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/back_end.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/inorder_back_end.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/pc_event.cc:
src/cpu/pc_event.hh:
src/cpu/profile.cc:
src/cpu/profile.hh:
src/cpu/quiesce_event.cc:
src/cpu/quiesce_event.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
src/cpu/thread_state.hh:
src/dev/alpha_console.cc:
src/dev/ns_gige.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/linux/events.cc:
src/kern/linux/events.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/kern/tru64/dump_mbuf.cc:
src/kern/tru64/tru64.hh:
src/kern/tru64/tru64_events.cc:
src/kern/tru64/tru64_events.hh:
src/mem/vport.cc:
src/mem/vport.hh:
src/sim/faults.cc:
src/sim/faults.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
src/sim/system.cc:
src/cpu/thread_context.hh:
src/sim/system.hh:
src/sim/vptr.hh:
    Change ExecContext to ThreadContext.

--HG--
rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh
extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e
2006-06-06 17:32:21 -04:00
Ali Saidi
cb0cf2dd8a Updated Authors from bk prs info
--HG--
extra : convert_revision : 77f475b156d81c03a2811818fa23593d5615c685
2006-05-31 19:26:56 -04:00
Ali Saidi
4d8ea8dc47 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : ebd55fc18b09821712f73867c93bd3d888e7788c
2006-05-31 13:47:35 -04:00
Ali Saidi
0193c3fe7d make io device be a little nicer about scheduling retries on the bus
--HG--
extra : convert_revision : 19a1f0c7bf79d6d8ef235aae60cdbbbcb7de2b79
2006-05-31 13:45:37 -04:00
Steve Reinhardt
d77d39daee Streamline interface to Request object.
src/SConscript:
    mem/request.cc no longer needed (all functions inline).
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/timing.cc:
src/dev/io_device.cc:
src/mem/port.cc:
    Modified Request object interface.
src/mem/packet.hh:
    Modified Request object interface.
    Address & size are always set together now, so track
    with single flag.
src/mem/request.hh:
    Streamline interface to support a handful of calls that set
    multiple fields reflecting common usage patterns.
    Reduce number of validFoo booleans by combining flags for fields
    which must be set together.

--HG--
extra : convert_revision : 3b499de90d6d5f12f0cc7a9a788663265677fe10
2006-05-31 00:12:29 -04:00
Steve Reinhardt
91e3aa6295 Minor further cleanup & commenting of Packet class.
src/cpu/simple/atomic.cc:
    Make common ifetch setup based on Request rather than Packet.
    Packet::reset() no longer a separate function.
    sendAtomic() returns latency, not absolute tick.
src/cpu/simple/atomic.hh:
    sendAtomic returns latency, not absolute tick.
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
    Make common ifetch setup based on Request rather than Packet.
src/dev/alpha_console.cc:
src/dev/ide_ctrl.cc:
src/dev/io_device.cc:
src/dev/isa_fake.cc:
src/dev/ns_gige.cc:
src/dev/pciconfigall.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/dev/tsunami_io.cc:
src/dev/tsunami_pchip.cc:
src/dev/uart8250.cc:
src/mem/physical.cc:
    Get rid of redundant Packet time field.
src/mem/packet.cc:
    Eliminate reset() method.
src/mem/packet.hh:
    Fold reset() function into reinitFromRequest()... it was
    only ever called together with that function.
    Get rid of redundant time field.
    Cleanup/add comments.
src/mem/port.hh:
    Document in comment that sendAtomic returns latency, not absolute tick.

--HG--
extra : convert_revision : 0252f1a294043ca3ed58f437232ad24fc0733e0c
2006-05-30 22:30:42 -04:00
Ali Saidi
09d8a1e125 Add a very poor implementation of dealing with retries on timing requests. It is especially slow with tracing on since
it ends up being O(N^2). But it's probably going to have to change for the real bus anyway, so it should be rewritten then
Change recvRetry() to not accept a packet. Sendtiming should be called again (and can respond with false or true)
Removed Port Blocked/Unblocked and replaced with sendRetry().
Remove possibility of packet mangling if packet is going to be refused anyway in bridge

src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Change recvRetry() to not accept a packet. Sendtiming should be called again (and can respond with false or true)
src/dev/io_device.cc:
src/dev/io_device.hh:
    Make DMA Timing requests/responses work.
    Change recvRetry() to not accept a packet. Sendtiming should be called again (and can respond with false or true)
src/mem/bridge.cc:
src/mem/bridge.hh:
    Change recvRetry() to not accept a packet. Sendtiming should be called again (and can respond with false or true)
    Removed Port Blocked/Unblocked and replaced with sendRetry().
    Remove posibility of packet mangling if packet is going to be refused anyway.
src/mem/bus.cc:
src/mem/bus.hh:
    Add a very poor implementation of dealing with retries on timing requests. It is especially slow with tracing on since
    it ends up being O(N^2). But it's probably going to have to change for the real bus anyway, so it should be rewritten then
src/mem/port.hh:
    Change recvRetry() to not accept a packet. Sendtiming should be called again (and can respond with false or true)
    Removed Blocked/Unblocked port status, their functionality is really duplicated in the recvRetry() method

--HG--
extra : convert_revision : fab613404be54bfa7a4c67572bae7b559169e573
2006-05-30 18:57:42 -04:00
Ali Saidi
de20b819f1 remove some getPtr() calls by changing having function return values
instead of taking a pointer

--HG--
extra : convert_revision : fd9092eaa726e91b501334d35d28dda28aaa01bd
2006-05-28 22:21:57 -04:00
Steve Reinhardt
e533fad711 Significant rework of Packet class interface:
- new constructor guarantees initialization of most fields
- flags track status of non-guaranteed fields (addr, size, src)
- accessor functions (getAddr() etc.) check status on access
- Command & Result classes are nested in Packet class scope
- Command now built from vector of behavior bits
- string version of Command for tracing
- reinitFromRequest() and makeTimingResponse() encapsulate
common manipulations of existing packets

src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/timing.cc:
src/dev/alpha_console.cc:
src/dev/ide_ctrl.cc:
src/dev/io_device.cc:
src/dev/io_device.hh:
src/dev/isa_fake.cc:
src/dev/ns_gige.cc:
src/dev/pciconfigall.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/dev/tsunami_io.cc:
src/dev/tsunami_pchip.cc:
src/dev/uart8250.cc:
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/physical.cc:
src/mem/port.cc:
src/mem/port.hh:
src/mem/request.hh:
    Update for new Packet interface.

--HG--
extra : convert_revision : 9973d09ea4fa61795f23772a7d3995fa4df5c269
2006-05-26 14:17:33 -04:00
Steve Reinhardt
da6a7b1263 Add names to memory Port objects for tracing.
--HG--
extra : convert_revision : ddf30084e343e8656e4812ab20356292b35507ee
2006-05-26 13:48:35 -04:00
Steve Reinhardt
cf826ae296 Minor fixes for full-system timing memory.
Need to rewrite bus bridge to get any further.

src/dev/io_device.cc:
    Set packet dest on timing responses.
src/mem/bus.cc:
    Fix dest addr bounds check assertion.
    Add assertion to catch infinite loopbacks.
src/mem/physical.cc:
    Add comment.

--HG--
extra : convert_revision : 419b65a3a61e2d099884dbda117b338dffd80896
2006-05-23 17:16:45 -04:00
Steve Reinhardt
ba2eae5d52 New directory structure:
- simulator source now in 'src' subdirectory
- imported files from 'ext' repository
- support building in arbitrary places, including
outside of the source tree.  See comment at top
of SConstruct file for more details.
Regression tests are temporarily disabled; that
syetem needs more extensive revisions.

SConstruct:
    Update for new directory structure.
    Modify to support build trees that are not subdirectories
    of the source tree.  See comment at top of file for
    more details.
    Regression tests are temporarily disabled.
src/arch/SConscript:
src/arch/isa_parser.py:
src/python/SConscript:
    Update for new directory structure.

--HG--
rename : build/SConstruct => SConstruct
rename : build/default_options/ALPHA_FS => build_opts/ALPHA_FS
rename : build/default_options/ALPHA_FS_TL => build_opts/ALPHA_FS_TL
rename : build/default_options/ALPHA_SE => build_opts/ALPHA_SE
rename : build/default_options/MIPS_SE => build_opts/MIPS_SE
rename : build/default_options/SPARC_SE => build_opts/SPARC_SE
rename : Doxyfile => src/Doxyfile
rename : SConscript => src/SConscript
rename : arch/SConscript => src/arch/SConscript
rename : arch/alpha/SConscript => src/arch/alpha/SConscript
rename : arch/alpha/aout_machdep.h => src/arch/alpha/aout_machdep.h
rename : arch/alpha/arguments.cc => src/arch/alpha/arguments.cc
rename : arch/alpha/arguments.hh => src/arch/alpha/arguments.hh
rename : arch/alpha/ecoff_machdep.h => src/arch/alpha/ecoff_machdep.h
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/ev5.hh => src/arch/alpha/ev5.hh
rename : arch/alpha/faults.cc => src/arch/alpha/faults.cc
rename : arch/alpha/faults.hh => src/arch/alpha/faults.hh
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/freebsd/system.hh => src/arch/alpha/freebsd/system.hh
rename : arch/alpha/isa/branch.isa => src/arch/alpha/isa/branch.isa
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/fp.isa => src/arch/alpha/isa/fp.isa
rename : arch/alpha/isa/int.isa => src/arch/alpha/isa/int.isa
rename : arch/alpha/isa/main.isa => src/arch/alpha/isa/main.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa/opcdec.isa => src/arch/alpha/isa/opcdec.isa
rename : arch/alpha/isa/pal.isa => src/arch/alpha/isa/pal.isa
rename : arch/alpha/isa/unimp.isa => src/arch/alpha/isa/unimp.isa
rename : arch/alpha/isa/unknown.isa => src/arch/alpha/isa/unknown.isa
rename : arch/alpha/isa/util.isa => src/arch/alpha/isa/util.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/aligned.hh => src/arch/alpha/linux/aligned.hh
rename : arch/alpha/linux/hwrpb.hh => src/arch/alpha/linux/hwrpb.hh
rename : arch/alpha/linux/linux.cc => src/arch/alpha/linux/linux.cc
rename : arch/alpha/linux/linux.hh => src/arch/alpha/linux/linux.hh
rename : arch/alpha/linux/process.cc => src/arch/alpha/linux/process.cc
rename : arch/alpha/linux/process.hh => src/arch/alpha/linux/process.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/linux/system.hh => src/arch/alpha/linux/system.hh
rename : arch/alpha/linux/thread_info.hh => src/arch/alpha/linux/thread_info.hh
rename : arch/alpha/linux/threadinfo.hh => src/arch/alpha/linux/threadinfo.hh
rename : arch/alpha/osfpal.cc => src/arch/alpha/osfpal.cc
rename : arch/alpha/osfpal.hh => src/arch/alpha/osfpal.hh
rename : arch/alpha/process.cc => src/arch/alpha/process.cc
rename : arch/alpha/process.hh => src/arch/alpha/process.hh
rename : arch/alpha/regfile.hh => src/arch/alpha/regfile.hh
rename : arch/alpha/stacktrace.cc => src/arch/alpha/stacktrace.cc
rename : arch/alpha/stacktrace.hh => src/arch/alpha/stacktrace.hh
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/system.hh => src/arch/alpha/system.hh
rename : arch/alpha/tlb.cc => src/arch/alpha/tlb.cc
rename : arch/alpha/tlb.hh => src/arch/alpha/tlb.hh
rename : arch/alpha/tru64/process.cc => src/arch/alpha/tru64/process.cc
rename : arch/alpha/tru64/process.hh => src/arch/alpha/tru64/process.hh
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : arch/alpha/tru64/system.hh => src/arch/alpha/tru64/system.hh
rename : arch/alpha/tru64/tru64.cc => src/arch/alpha/tru64/tru64.cc
rename : arch/alpha/tru64/tru64.hh => src/arch/alpha/tru64/tru64.hh
rename : arch/alpha/types.hh => src/arch/alpha/types.hh
rename : arch/alpha/utility.hh => src/arch/alpha/utility.hh
rename : arch/alpha/vtophys.cc => src/arch/alpha/vtophys.cc
rename : arch/alpha/vtophys.hh => src/arch/alpha/vtophys.hh
rename : arch/isa_parser.py => src/arch/isa_parser.py
rename : arch/isa_specific.hh => src/arch/isa_specific.hh
rename : arch/mips/SConscript => src/arch/mips/SConscript
rename : arch/mips/faults.cc => src/arch/mips/faults.cc
rename : arch/mips/faults.hh => src/arch/mips/faults.hh
rename : arch/mips/isa/base.isa => src/arch/mips/isa/base.isa
rename : arch/mips/isa/bitfields.isa => src/arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.isa => src/arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats/basic.isa => src/arch/mips/isa/formats/basic.isa
rename : arch/mips/isa/formats/branch.isa => src/arch/mips/isa/formats/branch.isa
rename : arch/mips/isa/formats/formats.isa => src/arch/mips/isa/formats/formats.isa
rename : arch/mips/isa/formats/fp.isa => src/arch/mips/isa/formats/fp.isa
rename : arch/mips/isa/formats/int.isa => src/arch/mips/isa/formats/int.isa
rename : arch/mips/isa/formats/mem.isa => src/arch/mips/isa/formats/mem.isa
rename : arch/mips/isa/formats/noop.isa => src/arch/mips/isa/formats/noop.isa
rename : arch/mips/isa/formats/tlbop.isa => src/arch/mips/isa/formats/tlbop.isa
rename : arch/mips/isa/formats/trap.isa => src/arch/mips/isa/formats/trap.isa
rename : arch/mips/isa/formats/unimp.isa => src/arch/mips/isa/formats/unimp.isa
rename : arch/mips/isa/formats/unknown.isa => src/arch/mips/isa/formats/unknown.isa
rename : arch/mips/isa/formats/util.isa => src/arch/mips/isa/formats/util.isa
rename : arch/mips/isa/includes.isa => src/arch/mips/isa/includes.isa
rename : arch/mips/isa/main.isa => src/arch/mips/isa/main.isa
rename : arch/mips/isa/operands.isa => src/arch/mips/isa/operands.isa
rename : arch/mips/isa_traits.cc => src/arch/mips/isa_traits.cc
rename : arch/mips/isa_traits.hh => src/arch/mips/isa_traits.hh
rename : arch/mips/linux/linux.cc => src/arch/mips/linux/linux.cc
rename : arch/mips/linux/linux.hh => src/arch/mips/linux/linux.hh
rename : arch/mips/linux/process.cc => src/arch/mips/linux/process.cc
rename : arch/mips/linux/process.hh => src/arch/mips/linux/process.hh
rename : arch/mips/process.cc => src/arch/mips/process.cc
rename : arch/mips/process.hh => src/arch/mips/process.hh
rename : arch/mips/regfile/float_regfile.hh => src/arch/mips/regfile/float_regfile.hh
rename : arch/mips/regfile/int_regfile.hh => src/arch/mips/regfile/int_regfile.hh
rename : arch/mips/regfile/misc_regfile.hh => src/arch/mips/regfile/misc_regfile.hh
rename : arch/mips/regfile/regfile.hh => src/arch/mips/regfile/regfile.hh
rename : arch/mips/stacktrace.hh => src/arch/mips/stacktrace.hh
rename : arch/mips/types.hh => src/arch/mips/types.hh
rename : arch/mips/utility.hh => src/arch/mips/utility.hh
rename : arch/sparc/SConscript => src/arch/sparc/SConscript
rename : arch/sparc/faults.cc => src/arch/sparc/faults.cc
rename : arch/sparc/faults.hh => src/arch/sparc/faults.hh
rename : arch/sparc/isa/base.isa => src/arch/sparc/isa/base.isa
rename : arch/sparc/isa/bitfields.isa => src/arch/sparc/isa/bitfields.isa
rename : arch/sparc/isa/decoder.isa => src/arch/sparc/isa/decoder.isa
rename : arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats.isa
rename : arch/sparc/isa/formats/basic.isa => src/arch/sparc/isa/formats/basic.isa
rename : arch/sparc/isa/formats/branch.isa => src/arch/sparc/isa/formats/branch.isa
rename : arch/sparc/isa/formats/integerop.isa => src/arch/sparc/isa/formats/integerop.isa
rename : arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem.isa
rename : arch/sparc/isa/formats/nop.isa => src/arch/sparc/isa/formats/nop.isa
rename : arch/sparc/isa/formats/priv.isa => src/arch/sparc/isa/formats/priv.isa
rename : arch/sparc/isa/formats/trap.isa => src/arch/sparc/isa/formats/trap.isa
rename : arch/sparc/isa/formats/unknown.isa => src/arch/sparc/isa/formats/unknown.isa
rename : arch/sparc/isa/includes.isa => src/arch/sparc/isa/includes.isa
rename : arch/sparc/isa/main.isa => src/arch/sparc/isa/main.isa
rename : arch/sparc/isa/operands.isa => src/arch/sparc/isa/operands.isa
rename : arch/sparc/isa_traits.hh => src/arch/sparc/isa_traits.hh
rename : arch/sparc/linux/linux.cc => src/arch/sparc/linux/linux.cc
rename : arch/sparc/linux/linux.hh => src/arch/sparc/linux/linux.hh
rename : arch/sparc/linux/process.cc => src/arch/sparc/linux/process.cc
rename : arch/sparc/linux/process.hh => src/arch/sparc/linux/process.hh
rename : arch/sparc/process.cc => src/arch/sparc/process.cc
rename : arch/sparc/process.hh => src/arch/sparc/process.hh
rename : arch/sparc/regfile.hh => src/arch/sparc/regfile.hh
rename : arch/sparc/solaris/process.cc => src/arch/sparc/solaris/process.cc
rename : arch/sparc/solaris/process.hh => src/arch/sparc/solaris/process.hh
rename : arch/sparc/solaris/solaris.cc => src/arch/sparc/solaris/solaris.cc
rename : arch/sparc/solaris/solaris.hh => src/arch/sparc/solaris/solaris.hh
rename : arch/sparc/stacktrace.hh => src/arch/sparc/stacktrace.hh
rename : arch/sparc/system.cc => src/arch/sparc/system.cc
rename : arch/sparc/system.hh => src/arch/sparc/system.hh
rename : arch/sparc/utility.hh => src/arch/sparc/utility.hh
rename : base/bitfield.hh => src/base/bitfield.hh
rename : base/callback.hh => src/base/callback.hh
rename : base/chunk_generator.hh => src/base/chunk_generator.hh
rename : base/circlebuf.cc => src/base/circlebuf.cc
rename : base/circlebuf.hh => src/base/circlebuf.hh
rename : base/compression/lzss_compression.cc => src/base/compression/lzss_compression.cc
rename : base/compression/lzss_compression.hh => src/base/compression/lzss_compression.hh
rename : base/compression/null_compression.hh => src/base/compression/null_compression.hh
rename : base/cprintf.cc => src/base/cprintf.cc
rename : base/cprintf.hh => src/base/cprintf.hh
rename : base/cprintf_formats.hh => src/base/cprintf_formats.hh
rename : base/crc.cc => src/base/crc.cc
rename : base/crc.hh => src/base/crc.hh
rename : base/date.cc => src/base/date.cc
rename : base/dbl_list.hh => src/base/dbl_list.hh
rename : base/endian.hh => src/base/endian.hh
rename : base/fast_alloc.cc => src/base/fast_alloc.cc
rename : base/fast_alloc.hh => src/base/fast_alloc.hh
rename : base/fenv.hh => src/base/fenv.hh
rename : base/fifo_buffer.cc => src/base/fifo_buffer.cc
rename : base/fifo_buffer.hh => src/base/fifo_buffer.hh
rename : base/hashmap.hh => src/base/hashmap.hh
rename : base/hostinfo.cc => src/base/hostinfo.cc
rename : base/hostinfo.hh => src/base/hostinfo.hh
rename : base/hybrid_pred.cc => src/base/hybrid_pred.cc
rename : base/hybrid_pred.hh => src/base/hybrid_pred.hh
rename : base/inet.cc => src/base/inet.cc
rename : base/inet.hh => src/base/inet.hh
rename : base/inifile.cc => src/base/inifile.cc
rename : base/inifile.hh => src/base/inifile.hh
rename : base/intmath.cc => src/base/intmath.cc
rename : base/intmath.hh => src/base/intmath.hh
rename : base/kgdb.h => src/base/kgdb.h
rename : base/loader/aout_object.cc => src/base/loader/aout_object.cc
rename : base/loader/aout_object.hh => src/base/loader/aout_object.hh
rename : base/loader/coff_sym.h => src/base/loader/coff_sym.h
rename : base/loader/coff_symconst.h => src/base/loader/coff_symconst.h
rename : base/loader/ecoff_object.cc => src/base/loader/ecoff_object.cc
rename : base/loader/ecoff_object.hh => src/base/loader/ecoff_object.hh
rename : base/loader/elf_object.cc => src/base/loader/elf_object.cc
rename : base/loader/elf_object.hh => src/base/loader/elf_object.hh
rename : base/loader/exec_aout.h => src/base/loader/exec_aout.h
rename : base/loader/exec_ecoff.h => src/base/loader/exec_ecoff.h
rename : base/loader/object_file.cc => src/base/loader/object_file.cc
rename : base/loader/object_file.hh => src/base/loader/object_file.hh
rename : base/loader/symtab.cc => src/base/loader/symtab.cc
rename : base/loader/symtab.hh => src/base/loader/symtab.hh
rename : base/match.cc => src/base/match.cc
rename : base/match.hh => src/base/match.hh
rename : base/misc.cc => src/base/misc.cc
rename : base/misc.hh => src/base/misc.hh
rename : base/mod_num.hh => src/base/mod_num.hh
rename : base/mysql.cc => src/base/mysql.cc
rename : base/mysql.hh => src/base/mysql.hh
rename : base/output.cc => src/base/output.cc
rename : base/output.hh => src/base/output.hh
rename : base/pollevent.cc => src/base/pollevent.cc
rename : base/pollevent.hh => src/base/pollevent.hh
rename : base/predictor.hh => src/base/predictor.hh
rename : base/random.cc => src/base/random.cc
rename : base/random.hh => src/base/random.hh
rename : base/range.cc => src/base/range.cc
rename : base/range.hh => src/base/range.hh
rename : base/refcnt.hh => src/base/refcnt.hh
rename : base/remote_gdb.cc => src/base/remote_gdb.cc
rename : base/remote_gdb.hh => src/base/remote_gdb.hh
rename : base/res_list.hh => src/base/res_list.hh
rename : base/sat_counter.cc => src/base/sat_counter.cc
rename : base/sat_counter.hh => src/base/sat_counter.hh
rename : base/sched_list.hh => src/base/sched_list.hh
rename : base/socket.cc => src/base/socket.cc
rename : base/socket.hh => src/base/socket.hh
rename : base/statistics.cc => src/base/statistics.cc
rename : base/statistics.hh => src/base/statistics.hh
rename : base/stats/events.cc => src/base/stats/events.cc
rename : base/stats/events.hh => src/base/stats/events.hh
rename : base/stats/flags.hh => src/base/stats/flags.hh
rename : base/stats/mysql.cc => src/base/stats/mysql.cc
rename : base/stats/mysql.hh => src/base/stats/mysql.hh
rename : base/stats/mysql_run.hh => src/base/stats/mysql_run.hh
rename : base/stats/output.hh => src/base/stats/output.hh
rename : base/stats/statdb.cc => src/base/stats/statdb.cc
rename : base/stats/statdb.hh => src/base/stats/statdb.hh
rename : base/stats/text.cc => src/base/stats/text.cc
rename : base/stats/text.hh => src/base/stats/text.hh
rename : base/stats/types.hh => src/base/stats/types.hh
rename : base/stats/visit.cc => src/base/stats/visit.cc
rename : base/stats/visit.hh => src/base/stats/visit.hh
rename : base/str.cc => src/base/str.cc
rename : base/str.hh => src/base/str.hh
rename : base/time.cc => src/base/time.cc
rename : base/time.hh => src/base/time.hh
rename : base/timebuf.hh => src/base/timebuf.hh
rename : base/trace.cc => src/base/trace.cc
rename : base/trace.hh => src/base/trace.hh
rename : base/traceflags.py => src/base/traceflags.py
rename : base/userinfo.cc => src/base/userinfo.cc
rename : base/userinfo.hh => src/base/userinfo.hh
rename : cpu/SConscript => src/cpu/SConscript
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst.cc
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/cpu_exec_context.cc => src/cpu/cpu_exec_context.cc
rename : cpu/cpu_exec_context.hh => src/cpu/cpu_exec_context.hh
rename : cpu/cpu_models.py => src/cpu/cpu_models.py
rename : cpu/exec_context.hh => src/cpu/exec_context.hh
rename : cpu/exetrace.cc => src/cpu/exetrace.cc
rename : cpu/exetrace.hh => src/cpu/exetrace.hh
rename : cpu/inst_seq.hh => src/cpu/inst_seq.hh
rename : cpu/intr_control.cc => src/cpu/intr_control.cc
rename : cpu/intr_control.hh => src/cpu/intr_control.hh
rename : cpu/memtest/memtest.cc => src/cpu/memtest/memtest.cc
rename : cpu/memtest/memtest.hh => src/cpu/memtest/memtest.hh
rename : cpu/o3/2bit_local_pred.cc => src/cpu/o3/2bit_local_pred.cc
rename : cpu/o3/2bit_local_pred.hh => src/cpu/o3/2bit_local_pred.hh
rename : cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha_cpu.cc
rename : cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha_cpu.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha_cpu_builder.cc
rename : cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha_cpu_impl.hh
rename : cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha_dyn_inst.cc
rename : cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha_dyn_inst.hh
rename : cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/o3/alpha_impl.hh => src/cpu/o3/alpha_impl.hh
rename : cpu/o3/alpha_params.hh => src/cpu/o3/alpha_params.hh
rename : cpu/o3/bpred_unit.cc => src/cpu/o3/bpred_unit.cc
rename : cpu/o3/bpred_unit.hh => src/cpu/o3/bpred_unit.hh
rename : cpu/o3/bpred_unit_impl.hh => src/cpu/o3/bpred_unit_impl.hh
rename : cpu/o3/btb.cc => src/cpu/o3/btb.cc
rename : cpu/o3/btb.hh => src/cpu/o3/btb.hh
rename : cpu/o3/comm.hh => src/cpu/o3/comm.hh
rename : cpu/o3/commit.cc => src/cpu/o3/commit.cc
rename : cpu/o3/commit.hh => src/cpu/o3/commit.hh
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/cpu.hh => src/cpu/o3/cpu.hh
rename : cpu/o3/cpu_policy.hh => src/cpu/o3/cpu_policy.hh
rename : cpu/o3/decode.cc => src/cpu/o3/decode.cc
rename : cpu/o3/decode.hh => src/cpu/o3/decode.hh
rename : cpu/o3/decode_impl.hh => src/cpu/o3/decode_impl.hh
rename : cpu/o3/fetch.cc => src/cpu/o3/fetch.cc
rename : cpu/o3/fetch.hh => src/cpu/o3/fetch.hh
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/free_list.cc => src/cpu/o3/free_list.cc
rename : cpu/o3/free_list.hh => src/cpu/o3/free_list.hh
rename : cpu/o3/iew.cc => src/cpu/o3/iew.cc
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.cc => src/cpu/o3/inst_queue.cc
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/mem_dep_unit.cc => src/cpu/o3/mem_dep_unit.cc
rename : cpu/o3/mem_dep_unit.hh => src/cpu/o3/mem_dep_unit.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/ras.cc => src/cpu/o3/ras.cc
rename : cpu/o3/ras.hh => src/cpu/o3/ras.hh
rename : cpu/o3/regfile.hh => src/cpu/o3/regfile.hh
rename : cpu/o3/rename.cc => src/cpu/o3/rename.cc
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/rename_map.cc => src/cpu/o3/rename_map.cc
rename : cpu/o3/rename_map.hh => src/cpu/o3/rename_map.hh
rename : cpu/o3/rob.cc => src/cpu/o3/rob.cc
rename : cpu/o3/rob.hh => src/cpu/o3/rob.hh
rename : cpu/o3/rob_impl.hh => src/cpu/o3/rob_impl.hh
rename : cpu/o3/sat_counter.cc => src/cpu/o3/sat_counter.cc
rename : cpu/o3/sat_counter.hh => src/cpu/o3/sat_counter.hh
rename : cpu/o3/store_set.cc => src/cpu/o3/store_set.cc
rename : cpu/o3/store_set.hh => src/cpu/o3/store_set.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/op_class.cc => src/cpu/op_class.cc
rename : cpu/op_class.hh => src/cpu/op_class.hh
rename : cpu/ozone/cpu.cc => src/cpu/ozone/cpu.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/ea_list.cc => src/cpu/ozone/ea_list.cc
rename : cpu/ozone/ea_list.hh => src/cpu/ozone/ea_list.hh
rename : cpu/pc_event.cc => src/cpu/pc_event.cc
rename : cpu/pc_event.hh => src/cpu/pc_event.hh
rename : cpu/profile.cc => src/cpu/profile.cc
rename : cpu/profile.hh => src/cpu/profile.hh
rename : cpu/simple/atomic.cc => src/cpu/simple/atomic.cc
rename : cpu/simple/atomic.hh => src/cpu/simple/atomic.hh
rename : cpu/simple/base.cc => src/cpu/simple/base.cc
rename : cpu/simple/base.hh => src/cpu/simple/base.hh
rename : cpu/simple/timing.cc => src/cpu/simple/timing.cc
rename : cpu/simple/timing.hh => src/cpu/simple/timing.hh
rename : cpu/smt.hh => src/cpu/smt.hh
rename : cpu/static_inst.cc => src/cpu/static_inst.cc
rename : cpu/static_inst.hh => src/cpu/static_inst.hh
rename : cpu/trace/opt_cpu.cc => src/cpu/trace/opt_cpu.cc
rename : cpu/trace/opt_cpu.hh => src/cpu/trace/opt_cpu.hh
rename : cpu/trace/reader/ibm_reader.cc => src/cpu/trace/reader/ibm_reader.cc
rename : cpu/trace/reader/ibm_reader.hh => src/cpu/trace/reader/ibm_reader.hh
rename : cpu/trace/reader/itx_reader.cc => src/cpu/trace/reader/itx_reader.cc
rename : cpu/trace/reader/itx_reader.hh => src/cpu/trace/reader/itx_reader.hh
rename : cpu/trace/reader/m5_reader.cc => src/cpu/trace/reader/m5_reader.cc
rename : cpu/trace/reader/m5_reader.hh => src/cpu/trace/reader/m5_reader.hh
rename : cpu/trace/reader/mem_trace_reader.cc => src/cpu/trace/reader/mem_trace_reader.cc
rename : cpu/trace/reader/mem_trace_reader.hh => src/cpu/trace/reader/mem_trace_reader.hh
rename : cpu/trace/trace_cpu.cc => src/cpu/trace/trace_cpu.cc
rename : cpu/trace/trace_cpu.hh => src/cpu/trace/trace_cpu.hh
rename : dev/alpha_access.h => src/dev/alpha_access.h
rename : dev/alpha_console.cc => src/dev/alpha_console.cc
rename : dev/alpha_console.hh => src/dev/alpha_console.hh
rename : dev/baddev.cc => src/dev/baddev.cc
rename : dev/baddev.hh => src/dev/baddev.hh
rename : dev/disk_image.cc => src/dev/disk_image.cc
rename : dev/disk_image.hh => src/dev/disk_image.hh
rename : dev/etherbus.cc => src/dev/etherbus.cc
rename : dev/etherbus.hh => src/dev/etherbus.hh
rename : dev/etherdump.cc => src/dev/etherdump.cc
rename : dev/etherdump.hh => src/dev/etherdump.hh
rename : dev/etherint.cc => src/dev/etherint.cc
rename : dev/etherint.hh => src/dev/etherint.hh
rename : dev/etherlink.cc => src/dev/etherlink.cc
rename : dev/etherlink.hh => src/dev/etherlink.hh
rename : dev/etherpkt.cc => src/dev/etherpkt.cc
rename : dev/etherpkt.hh => src/dev/etherpkt.hh
rename : dev/ethertap.cc => src/dev/ethertap.cc
rename : dev/ethertap.hh => src/dev/ethertap.hh
rename : dev/ide_atareg.h => src/dev/ide_atareg.h
rename : dev/ide_ctrl.cc => src/dev/ide_ctrl.cc
rename : dev/ide_ctrl.hh => src/dev/ide_ctrl.hh
rename : dev/ide_disk.cc => src/dev/ide_disk.cc
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : dev/ide_wdcreg.h => src/dev/ide_wdcreg.h
rename : dev/io_device.cc => src/dev/io_device.cc
rename : dev/io_device.hh => src/dev/io_device.hh
rename : dev/isa_fake.cc => src/dev/isa_fake.cc
rename : dev/isa_fake.hh => src/dev/isa_fake.hh
rename : dev/ns_gige.cc => src/dev/ns_gige.cc
rename : dev/ns_gige.hh => src/dev/ns_gige.hh
rename : dev/ns_gige_reg.h => src/dev/ns_gige_reg.h
rename : dev/pciconfigall.cc => src/dev/pciconfigall.cc
rename : dev/pciconfigall.hh => src/dev/pciconfigall.hh
rename : dev/pcidev.cc => src/dev/pcidev.cc
rename : dev/pcidev.hh => src/dev/pcidev.hh
rename : dev/pcireg.h => src/dev/pcireg.h
rename : dev/pitreg.h => src/dev/pitreg.h
rename : dev/pktfifo.cc => src/dev/pktfifo.cc
rename : dev/pktfifo.hh => src/dev/pktfifo.hh
rename : dev/platform.cc => src/dev/platform.cc
rename : dev/platform.hh => src/dev/platform.hh
rename : dev/rtcreg.h => src/dev/rtcreg.h
rename : dev/simconsole.cc => src/dev/simconsole.cc
rename : dev/simconsole.hh => src/dev/simconsole.hh
rename : dev/simple_disk.cc => src/dev/simple_disk.cc
rename : dev/simple_disk.hh => src/dev/simple_disk.hh
rename : dev/sinic.cc => src/dev/sinic.cc
rename : dev/sinic.hh => src/dev/sinic.hh
rename : dev/sinicreg.hh => src/dev/sinicreg.hh
rename : dev/tsunami.cc => src/dev/tsunami.cc
rename : dev/tsunami.hh => src/dev/tsunami.hh
rename : dev/tsunami_cchip.cc => src/dev/tsunami_cchip.cc
rename : dev/tsunami_cchip.hh => src/dev/tsunami_cchip.hh
rename : dev/tsunami_io.cc => src/dev/tsunami_io.cc
rename : dev/tsunami_io.hh => src/dev/tsunami_io.hh
rename : dev/tsunami_pchip.cc => src/dev/tsunami_pchip.cc
rename : dev/tsunami_pchip.hh => src/dev/tsunami_pchip.hh
rename : dev/tsunamireg.h => src/dev/tsunamireg.h
rename : dev/uart.cc => src/dev/uart.cc
rename : dev/uart.hh => src/dev/uart.hh
rename : dev/uart8250.cc => src/dev/uart8250.cc
rename : dev/uart8250.hh => src/dev/uart8250.hh
rename : kern/kernel_stats.cc => src/kern/kernel_stats.cc
rename : kern/kernel_stats.hh => src/kern/kernel_stats.hh
rename : kern/linux/events.cc => src/kern/linux/events.cc
rename : kern/linux/events.hh => src/kern/linux/events.hh
rename : kern/linux/linux.hh => src/kern/linux/linux.hh
rename : kern/linux/linux_syscalls.cc => src/kern/linux/linux_syscalls.cc
rename : kern/linux/linux_syscalls.hh => src/kern/linux/linux_syscalls.hh
rename : kern/linux/printk.cc => src/kern/linux/printk.cc
rename : kern/linux/printk.hh => src/kern/linux/printk.hh
rename : kern/linux/sched.hh => src/kern/linux/sched.hh
rename : kern/solaris/solaris.hh => src/kern/solaris/solaris.hh
rename : kern/system_events.cc => src/kern/system_events.cc
rename : kern/system_events.hh => src/kern/system_events.hh
rename : kern/tru64/dump_mbuf.cc => src/kern/tru64/dump_mbuf.cc
rename : kern/tru64/dump_mbuf.hh => src/kern/tru64/dump_mbuf.hh
rename : kern/tru64/mbuf.hh => src/kern/tru64/mbuf.hh
rename : kern/tru64/printf.cc => src/kern/tru64/printf.cc
rename : kern/tru64/printf.hh => src/kern/tru64/printf.hh
rename : kern/tru64/tru64.hh => src/kern/tru64/tru64.hh
rename : kern/tru64/tru64_events.cc => src/kern/tru64/tru64_events.cc
rename : kern/tru64/tru64_events.hh => src/kern/tru64/tru64_events.hh
rename : kern/tru64/tru64_syscalls.cc => src/kern/tru64/tru64_syscalls.cc
rename : kern/tru64/tru64_syscalls.hh => src/kern/tru64/tru64_syscalls.hh
rename : mem/bridge.cc => src/mem/bridge.cc
rename : mem/bridge.hh => src/mem/bridge.hh
rename : mem/bus.cc => src/mem/bus.cc
rename : mem/bus.hh => src/mem/bus.hh
rename : mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher_impl.hh
rename : mem/config/prefetch.hh => src/mem/config/prefetch.hh
rename : mem/mem_object.cc => src/mem/mem_object.cc
rename : mem/mem_object.hh => src/mem/mem_object.hh
rename : mem/packet.cc => src/mem/packet.cc
rename : mem/packet.hh => src/mem/packet.hh
rename : mem/page_table.cc => src/mem/page_table.cc
rename : mem/page_table.hh => src/mem/page_table.hh
rename : mem/physical.cc => src/mem/physical.cc
rename : mem/physical.hh => src/mem/physical.hh
rename : mem/port.cc => src/mem/port.cc
rename : mem/port.hh => src/mem/port.hh
rename : mem/request.hh => src/mem/request.hh
rename : mem/translating_port.cc => src/mem/translating_port.cc
rename : mem/translating_port.hh => src/mem/translating_port.hh
rename : mem/vport.cc => src/mem/vport.cc
rename : mem/vport.hh => src/mem/vport.hh
rename : python/SConscript => src/python/SConscript
rename : python/m5/__init__.py => src/python/m5/__init__.py
rename : python/m5/config.py => src/python/m5/config.py
rename : python/m5/convert.py => src/python/m5/convert.py
rename : python/m5/multidict.py => src/python/m5/multidict.py
rename : python/m5/objects/AlphaConsole.py => src/python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.py => src/python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.py => src/python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.py => src/python/m5/objects/BaseCache.py
rename : python/m5/objects/Bridge.py => src/python/m5/objects/Bridge.py
rename : python/m5/objects/Bus.py => src/python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.py => src/python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.py => src/python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.py => src/python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.py => src/python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.py => src/python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.py => src/python/m5/objects/IntrControl.py
rename : python/m5/objects/MemObject.py => src/python/m5/objects/MemObject.py
rename : python/m5/objects/MemTest.py => src/python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.py => src/python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.py => src/python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.py => src/python/m5/objects/Platform.py
rename : python/m5/objects/Process.py => src/python/m5/objects/Process.py
rename : python/m5/objects/Repl.py => src/python/m5/objects/Repl.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.py => src/python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.py => src/python/m5/objects/SimpleDisk.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : python/m5/objects/Tsunami.py => src/python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.py => src/python/m5/objects/Uart.py
rename : python/m5/smartdict.py => src/python/m5/smartdict.py
rename : sim/async.hh => src/sim/async.hh
rename : sim/builder.cc => src/sim/builder.cc
rename : sim/builder.hh => src/sim/builder.hh
rename : sim/byteswap.hh => src/sim/byteswap.hh
rename : sim/debug.cc => src/sim/debug.cc
rename : sim/debug.hh => src/sim/debug.hh
rename : sim/eventq.cc => src/sim/eventq.cc
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/faults.cc => src/sim/faults.cc
rename : sim/faults.hh => src/sim/faults.hh
rename : sim/host.hh => src/sim/host.hh
rename : sim/main.cc => src/sim/main.cc
rename : sim/param.cc => src/sim/param.cc
rename : sim/param.hh => src/sim/param.hh
rename : sim/process.cc => src/sim/process.cc
rename : sim/process.hh => src/sim/process.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/root.cc => src/sim/root.cc
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/serialize.hh => src/sim/serialize.hh
rename : sim/sim_events.cc => src/sim/sim_events.cc
rename : sim/sim_events.hh => src/sim/sim_events.hh
rename : sim/sim_exit.hh => src/sim/sim_exit.hh
rename : sim/sim_object.cc => src/sim/sim_object.cc
rename : sim/sim_object.hh => src/sim/sim_object.hh
rename : sim/startup.cc => src/sim/startup.cc
rename : sim/startup.hh => src/sim/startup.hh
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/stats.hh => src/sim/stats.hh
rename : sim/syscall_emul.cc => src/sim/syscall_emul.cc
rename : sim/syscall_emul.hh => src/sim/syscall_emul.hh
rename : sim/system.cc => src/sim/system.cc
rename : sim/system.hh => src/sim/system.hh
rename : sim/vptr.hh => src/sim/vptr.hh
rename : test/Makefile => src/unittest/Makefile
rename : test/bitvectest.cc => src/unittest/bitvectest.cc
rename : test/circletest.cc => src/unittest/circletest.cc
rename : test/cprintftest.cc => src/unittest/cprintftest.cc
rename : test/foo.ini => src/unittest/foo.ini
rename : test/genini.py => src/unittest/genini.py
rename : test/initest.cc => src/unittest/initest.cc
rename : test/initest.ini => src/unittest/initest.ini
rename : test/lru_test.cc => src/unittest/lru_test.cc
rename : test/nmtest.cc => src/unittest/nmtest.cc
rename : test/offtest.cc => src/unittest/offtest.cc
rename : test/paramtest.cc => src/unittest/paramtest.cc
rename : test/rangetest.cc => src/unittest/rangetest.cc
rename : test/sized_test.cc => src/unittest/sized_test.cc
rename : test/stattest.cc => src/unittest/stattest.cc
rename : test/strnumtest.cc => src/unittest/strnumtest.cc
rename : test/symtest.cc => src/unittest/symtest.cc
rename : test/tokentest.cc => src/unittest/tokentest.cc
rename : test/tracetest.cc => src/unittest/tracetest.cc
extra : convert_revision : cab6a5271ca1b368193cd948e5d3dcc47ab1bd48
2006-05-22 14:29:33 -04:00