sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
7676 commits 2 branches 0 tags 204 MiB
Commit graph

7676 commits

This branch
This branch
All branches
Author SHA1 Message Date
Gabe Black
f6182f948b X86: Make the TLB fault instead of panic when something is unmapped in SE mode. 
The fault object, if invoked, would then panic. This is a bit less direct, but
it means speculative execution won't panic the simulator.
 2010-08-23 09:44:19 -07:00
Gabe Black
172e45fc97 X86: Make the x86 ExtMachInst serializable with (UN)SERIALIZE_SCALAR. 
--HG--
rename : src/arch/x86/types.hh => src/arch/x86/types.cc
 2010-08-23 09:44:19 -07:00
Gabe Black
249549f9c3 X86: Define a noop ExtMachInst. 2010-08-23 09:44:19 -07:00
Gabe Black
d43eb42d00 X86: Mark serializing macroops and regular instructions as such. 2010-08-23 09:44:19 -07:00
Gabe Black
69fc2af006 X86: Add a .serializing directive that makes a macroop serializing. 
This directive really just tells the macroop to set IsSerializing and
IsSerializeAfter on its final microop.
 2010-08-23 09:44:19 -07:00
Gabe Black
5a1dbe4d99 X86: Consolidate extra microop flags into one parameter. 
This single parameter replaces the collection of bools that set up various
flavors of microops. A flag parameter also allows other flags to be set like
the serialize before/after flags, etc., without having to change the
constructor.
 2010-08-23 09:44:19 -07:00
Gabe Black
b187e7c9cc CPU: Make the constants for StaticInst flags visible outside the class. 2010-08-23 09:44:19 -07:00
Ali Saidi
6f24da359f BUILD: GCC 4.4.1/2 have a bug in their auto-vectorizer that we trip on 2010-08-23 11:18:42 -05:00
Ali Saidi
03584ad439 ALPHA: The previous O3 patch causes a slight stats change with fullsys. 2010-08-23 11:18:42 -05:00
Min Kyu Jeong
d8d6b869a2 O3: Skipping mem-order violation check for uncachable loads. 
Uncachable load is not executed until it reaches the head of the ROB,
hence cannot cause one.
 2010-08-23 11:18:42 -05:00
Min Kyu Jeong
e6a0be648e ARM: Improve printing of uop disassembly. 2010-08-23 11:18:42 -05:00
Min Kyu Jeong
d2fac84b95 ARM: Clean up flattening for SPSR adding 2010-08-23 11:18:41 -05:00
Gene Wu
a02d82f9f8 ARM: Implement DBG instruction that doesn't do much for now. 2010-08-23 11:18:41 -05:00
Gene Wu
d6736384b2 MEM: Make CLREX a first class request operation and clear locks in caches when it in received 2010-08-23 11:18:41 -05:00
Gene Wu
23626d99af ARM: Make sure that software prefetch instructions can't change the state of the TLB 2010-08-23 11:18:41 -05:00
Gene Wu
1fd104fc35 ARM: Don't write tracedata on writes, it might have been freed already. 2010-08-23 11:18:41 -05:00
Gene Wu
9db2ab8a62 ARM: Implement CLREX init/complete acc methods 2010-08-23 11:18:41 -05:00
Gene Wu
f29e09746a ARM: Fix Uncachable TLB requests and decoding of xn bit 2010-08-23 11:18:41 -05:00
Gene Wu
4b9de42439 Devices: Allow a device to specify that a request is uncachable. 2010-08-23 11:18:41 -05:00
Gene Wu
aa601750f8 ARM: For non-cachable accesses set the UNCACHABLE flag 2010-08-23 11:18:41 -05:00
Gene Wu
7405f4b774 ARM: Implement DSB, DMB, ISB 2010-08-23 11:18:41 -05:00
Gene Wu
aabf478920 ARM: Get SCTLR TE bit from reset SCTLR 2010-08-23 11:18:41 -05:00
Gene Wu
1f032ad345 ARM: Implement CLREX 2010-08-23 11:18:41 -05:00
Gene Wu
66bcbec96e ARM: BX instruction can be contitional if last instruction in a IT block 
Branches are allowed to be the last instuction in an IT block. Before it was
assumed that they could not. So Branches in thumb2 were Uncond.
 2010-08-23 11:18:41 -05:00
Min Kyu Jeong
ad2c3b008d CPU: Print out flatten-out register index as with IntRegs/FloatRegs traceflag 2010-08-23 11:18:41 -05:00
Min Kyu Jeong
03286e9d4e CPU: Make Exec trace to print predication result (if false) for memory instructions 2010-08-23 11:18:41 -05:00
Min Kyu Jeong
92ae620be8 ARM: mark msr/mrs instructions as SerializeBefore/After 
Since miscellaneous registers bypass wakeup logic, force serialization
to resolve data dependencies through them
* * *
ARM: adding non-speculative/serialize flags for instructions change CPSR
 2010-08-23 11:18:41 -05:00
Min Kyu Jeong
43c938d23e O3: Handle loads when the destination is the PC. 
For loads that PC is the destination, check if the load
was mispredicted again when the value being loaded returns from memory
 2010-08-23 11:18:40 -05:00
Min Kyu Jeong
5f91ec3f46 ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate. 
THis allows the CPU to handle predicated-false instructions accordingly.
This particular patch makes loads that are predicated-false to be sent
straight to the commit stage directly, not waiting for return of the data
that was never requested since it was predicated-false.
 2010-08-23 11:18:40 -05:00
Min Kyu Jeong
7acf67971c ARM: adding genMachineCheckFault() stub for ARM that doesn't panic 2010-08-23 11:18:40 -05:00
Gene Wu
5486fa6612 ARM: DFSR status value for sync external data abort is expected to be 0x8 in ARMv7 2010-08-23 11:18:40 -05:00
Gene Wu
a993188034 ARM: Temporary local variables can't conflict with isa parser operands. 
PC is an operand, so we can't have a temp called PC
 2010-08-23 11:18:40 -05:00
Ali Saidi
0c434b7f56 ARM: Exclusive accesses must be double word aligned 2010-08-23 11:18:40 -05:00
Ali Saidi
5148c693d8 ARM: Add some registers for big loads/stores to support neon. 2010-08-23 11:18:40 -05:00
Ali Saidi
fc1730044e ARM: Decode neon memory instructions. 2010-08-23 11:18:40 -05:00
Gabe Black
d1362d582a ARM: Clean up the ISA desc portion of the ARM memory instructions. 2010-08-23 11:18:40 -05:00
Ali Saidi
ef3a3dc28a Loader: Don't insert symbols into the symbol table that begin wiht '$'. 2010-08-23 11:18:40 -05:00
Ali Saidi
230acc291c ARM: We don't currently support ThumbEE exceptions, so don't report that we do 2010-08-23 11:18:40 -05:00
Ali Saidi
c0ca01ec36 ARM: Change how the AMBA device ID checking is done to make it more generic 2010-08-23 11:18:40 -05:00
Ali Saidi
330fada1aa ARM: Add configuration for Linux/Full System 2010-08-23 11:18:40 -05:00
Ali Saidi
bb5377899a ARM: Add system for ARM/Linux and bootstrapping 2010-08-23 11:18:40 -05:00
Ali Saidi
8ed4f0a02c ARM: Add I/O devices for booting linux 
--HG--
rename : src/dev/arm/Versatile.py => src/dev/arm/RealView.py
rename : src/dev/arm/versatile.cc => src/dev/arm/realview.cc
rename : src/dev/arm/versatile.hh => src/dev/arm/realview.hh
 2010-08-23 11:18:40 -05:00
Ali Saidi
38cf6a164d ARM: Implement some more misc registers 2010-08-23 11:18:40 -05:00
Ali Saidi
b7b2eae6fa ARM: Fix an un-initialized variable bug 2010-08-23 11:18:39 -05:00
Ali Saidi
4ab68fc999 Loader: Use address mask provided to load*Symbols when loading the symbols from the symbol table. 2010-08-23 11:18:39 -05:00
Ali Saidi
f2642e2055 Loader: Make the load address mask be a parameter of the system rather than a constant. 
This allows one two different OS requirements for the same ISA to be handled.
Some OSes are compiled for a virtual address and need to be loaded into physical
memory that starts at address 0, while other bare metal tools generate
images that start at address 0.
 2010-08-23 11:18:39 -05:00
Min Kyu Jeong
d4e83a4001 ARM: Finish the timing translation when taking a fault. 2010-08-23 11:18:39 -05:00
Dam Sunwoo
cb76111a7e ARM: Use a stl queue for the table walker state 2010-08-23 11:18:39 -05:00
Ali Saidi
1d1837ee98 CPU: Set a default value when readBytes faults. 
This was being done in read(), but if readBytes was called directly it
wouldn't happen. Also, instead of setting the memory blob being read to -1
which would (I believe) require using memset with -1 as a parameter, this now
uses bzero. It's hoped that it's more specialized behavior will make it
slightly faster.
 2010-08-23 11:18:39 -05:00
Ali Saidi
ac575a9d82 Compiler: Fixes for GCC 4.5. 2010-08-23 11:18:39 -05:00