Commit graph

11 commits

Author SHA1 Message Date
Andreas Sandberg 447a6b6442 stats: Update switcheroo reference stats
The Minor draining fixes affect perturb the timing slightly since it
affects how the simulator is drained. Update reference statistics to
reflect this expected change.
2015-07-31 17:04:59 +01:00
Andreas Sandberg c50e429001 stats: Bump stats after Minor switcheroo inclusion 2015-07-30 10:16:36 +01:00
Andreas Hansson 25e1b1c1f5 stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
2015-07-03 10:15:03 -04:00
Andreas Hansson a22c29b263 arm, stats: Update stats to reflect reduction in misc reg reads 2015-05-26 03:21:44 -04:00
Andreas Hansson 80cd107e51 stats: Update stats to reflect cache changes 2015-05-05 03:22:39 -04:00
Steve Reinhardt 0cf36d9409 stats: update for previous changeset
Very small differences in IQ-specific O3 stats.
2015-04-22 20:22:29 -07:00
Nilay Vaish 99fb8f8140 stats: changes to due to recent set of patches 2015-03-09 09:39:09 -05:00
Andreas Hansson 8909843a76 stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 05:04:20 -05:00
Andreas Hansson df8df4fd0a stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
2014-12-23 09:31:20 -05:00
Andreas Hansson 6489598fb4 stats: Bump stats for fixes, mostly TLB and WriteInvalidate 2014-12-02 06:08:25 -05:00
Ali Saidi 29cd50e14e arm, tests: Add 64-bit ARM regression tests 2014-10-29 23:50:15 -05:00