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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
Andreas Hansson 25e1b1c1f5 stats: Update stats for cache, crossbar and DRAM changes 
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
2015-07-03 10:15:03 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 51.235006 # Number of seconds simulated
sim_ticks 51235005618500 # Number of ticks simulated
final_tick 51235005618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 299120 # Simulator instruction rate (inst/s)
host_op_rate 351506 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 17342892504 # Simulator tick rate (ticks/s)
host_mem_usage 728488 # Number of bytes of host memory used
host_seconds 2954.24 # Real time elapsed on the host
sim_insts 883670074 # Number of instructions simulated
sim_ops 1038432543 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 126592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 125376 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 2934708 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 51720008 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 38784 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 35712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 741632 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 9002048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 95296 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker 86336 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 2270528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 22315456 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 419776 # Number of bytes read from this memory
system.physmem.bytes_read::total 89912252 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 2934708 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 741632 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 2270528 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5946868 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 77430208 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::total 77450788 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1978 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1959 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 86262 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 808138 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 606 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 558 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 11588 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 140657 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 1489 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker 1349 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 35477 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 348679 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6559 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1445299 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1209847 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1212420 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 2471 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 2447 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 57279 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1009466 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 757 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 697 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 14475 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 175701 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 1860 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker 1685 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 44316 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 435551 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8193 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1754899 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 57279 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 14475 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 44316 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 116070 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1511275 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 402 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1511677 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1511275 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 2471 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 2447 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 57279 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1009868 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 757 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 697 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 14475 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 175701 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 1860 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker 1685 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 44316 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 435551 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8193 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3266576 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 540590 # Number of read requests accepted
system.physmem.writeReqs 467319 # Number of write requests accepted
system.physmem.readBursts 540590 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 467319 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 34576064 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 21696 # Total number of bytes read from write queue
system.physmem.bytesWritten 29908416 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 34597760 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 29908416 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 339 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 52057 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 34722 # Per bank write bursts
system.physmem.perBankRdBursts::1 34925 # Per bank write bursts
system.physmem.perBankRdBursts::2 34806 # Per bank write bursts
system.physmem.perBankRdBursts::3 34433 # Per bank write bursts
system.physmem.perBankRdBursts::4 35553 # Per bank write bursts
system.physmem.perBankRdBursts::5 39917 # Per bank write bursts
system.physmem.perBankRdBursts::6 33295 # Per bank write bursts
system.physmem.perBankRdBursts::7 34606 # Per bank write bursts
system.physmem.perBankRdBursts::8 31417 # Per bank write bursts
system.physmem.perBankRdBursts::9 34834 # Per bank write bursts
system.physmem.perBankRdBursts::10 32861 # Per bank write bursts
system.physmem.perBankRdBursts::11 34723 # Per bank write bursts
system.physmem.perBankRdBursts::12 29445 # Per bank write bursts
system.physmem.perBankRdBursts::13 31855 # Per bank write bursts
system.physmem.perBankRdBursts::14 31705 # Per bank write bursts
system.physmem.perBankRdBursts::15 31154 # Per bank write bursts
system.physmem.perBankWrBursts::0 29588 # Per bank write bursts
system.physmem.perBankWrBursts::1 28520 # Per bank write bursts
system.physmem.perBankWrBursts::2 28987 # Per bank write bursts
system.physmem.perBankWrBursts::3 29728 # Per bank write bursts
system.physmem.perBankWrBursts::4 31002 # Per bank write bursts
system.physmem.perBankWrBursts::5 33624 # Per bank write bursts
system.physmem.perBankWrBursts::6 29096 # Per bank write bursts
system.physmem.perBankWrBursts::7 30620 # Per bank write bursts
system.physmem.perBankWrBursts::8 28064 # Per bank write bursts
system.physmem.perBankWrBursts::9 30877 # Per bank write bursts
system.physmem.perBankWrBursts::10 28622 # Per bank write bursts
system.physmem.perBankWrBursts::11 29758 # Per bank write bursts
system.physmem.perBankWrBursts::12 25484 # Per bank write bursts
system.physmem.perBankWrBursts::13 27499 # Per bank write bursts
system.physmem.perBankWrBursts::14 28130 # Per bank write bursts
system.physmem.perBankWrBursts::15 27720 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
system.physmem.totGap 51233860786000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 540590 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 467319 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 342994 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 115802 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 50344 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 30801 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 151 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 25 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 24 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 11 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 486 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 476 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 475 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 473 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 472 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 470 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 469 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 465 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 464 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 465 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 464 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 457 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 463 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 456 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 455 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 6847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 7567 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 16514 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 20463 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 25091 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 27451 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 27607 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 28499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 29120 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 30157 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 29862 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 30268 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 29365 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 30568 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 32780 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 28599 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 28666 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 27259 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 393 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 277 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 256 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 172 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 192 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 216 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 97 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 112 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 70 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 80 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 69 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 40 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 34 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 258364 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 249.586227 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 149.482668 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 288.931122 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 115624 44.75% 44.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 63401 24.54% 69.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 24271 9.39% 78.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 12099 4.68% 83.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 9378 3.63% 87.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 5671 2.19% 89.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 4999 1.93% 91.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3884 1.50% 92.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 19037 7.37% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 258364 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 26815 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 20.147343 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 9.386417 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-15 3084 11.50% 11.50% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::16-31 21562 80.41% 91.91% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32-47 1686 6.29% 98.20% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::48-63 338 1.26% 99.46% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::64-79 91 0.34% 99.80% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::80-95 28 0.10% 99.90% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::96-111 17 0.06% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::112-127 4 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::128-143 2 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::160-175 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::240-255 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::288-303 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 26815 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 26815 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.427522 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.974087 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 6.290252 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 17 0.06% 0.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 10 0.04% 0.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 10 0.04% 0.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 46 0.17% 0.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 25300 94.35% 94.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 507 1.89% 96.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 249 0.93% 97.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 127 0.47% 97.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 87 0.32% 98.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 125 0.47% 98.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 58 0.22% 98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 14 0.05% 99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 19 0.07% 99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 19 0.07% 99.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 12 0.04% 99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 8 0.03% 99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 123 0.46% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 19 0.07% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 20 0.07% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 17 0.06% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 6 0.02% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 3 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.00% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 6 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 2 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 3 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 26815 # Writes before turning the bus around for reads
system.physmem.totQLat 12836932182 # Total ticks spent queuing
system.physmem.totMemAccLat 22966638432 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2701255000 # Total ticks spent in databus transfers
system.physmem.avgQLat 23761.05 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 42511.05 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 0.67 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.58 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 0.68 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.58 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.01 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
system.physmem.avgWrQLen 22.63 # Average write queue length when enqueuing
system.physmem.readRowHits 422337 # Number of row buffer hits during reads
system.physmem.writeRowHits 326863 # Number of row buffer hits during writes
system.physmem.readRowHitRate 78.17 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 69.94 # Row buffer hit rate for writes
system.physmem.avgGap 50831831.83 # Average gap between requests
system.physmem.pageHitRate 74.36 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1022081760 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 555373500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2201604600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 1562664960 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3304577109600 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1165623840135 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29580668399250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34056211073805 # Total energy per rank (pJ)
system.physmem_0.averagePower 667.700210 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 48799941577250 # Time in different power states
system.physmem_0.memoryStateTime::REF 1689456600000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 106076762500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 931059360 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 506149875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 2012353200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 1465445520 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3304577109600 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1160291732670 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29572164937500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34041948787725 # Total energy per rank (pJ)
system.physmem_1.averagePower 667.708167 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 48807751567992 # Time in different power states
system.physmem_1.memoryStateTime::REF 1689456600000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 98247859258 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu2.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 196 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu2.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu2.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu2.inst 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu2.inst 1 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu2.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 112814 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 112814 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 112814 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 112814 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 112814 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 1116892952476 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.571172 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.494909 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 478954833976 42.88% 42.88% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 637938118500 57.12% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 1116892952476 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 81756 84.41% 84.41% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 15104 15.59% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 96860 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 112814 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 112814 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96860 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96860 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 209674 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 78427319 # DTB read hits
system.cpu0.dtb.read_misses 84483 # DTB read misses
system.cpu0.dtb.write_hits 71558713 # DTB write hits
system.cpu0.dtb.write_misses 28331 # DTB write misses
system.cpu0.dtb.flush_tlb 1285 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 21339 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 502 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 51365 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 3702 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 9826 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 78511802 # DTB read accesses
system.cpu0.dtb.write_accesses 71587044 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 149986032 # DTB hits
system.cpu0.dtb.misses 112814 # DTB misses
system.cpu0.dtb.accesses 150098846 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 63116 # Table walker walks requested
system.cpu0.itb.walker.walksLong 63116 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples 63116 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 63116 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 63116 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 1116892951476 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.571207 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.494904 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 478916115976 42.88% 42.88% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 637976835500 57.12% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 1116892951476 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 54727 95.15% 95.15% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 2791 4.85% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 57518 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 63116 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 63116 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57518 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57518 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 120634 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 420544157 # ITB inst hits
system.cpu0.itb.inst_misses 63116 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 1285 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 21339 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 502 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 35909 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 420607273 # ITB inst accesses
system.cpu0.itb.hits 420544157 # DTB hits
system.cpu0.itb.misses 63116 # DTB misses
system.cpu0.itb.accesses 420607273 # DTB accesses
system.cpu0.numCycles 505895917 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 420346594 # Number of instructions committed
system.cpu0.committedOps 494579830 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 453915139 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 407993 # Number of float alu accesses
system.cpu0.num_func_calls 25255441 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 64064604 # number of instructions that are conditional controls
system.cpu0.num_int_insts 453915139 # number of integer instructions
system.cpu0.num_fp_insts 407993 # number of float instructions
system.cpu0.num_int_register_reads 669796814 # number of times the integer registers were read
system.cpu0.num_int_register_writes 361015506 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 660600 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 338556 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 110996958 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 110750515 # number of times the CC registers were written
system.cpu0.num_mem_refs 150079107 # number of memory refs
system.cpu0.num_load_insts 78499668 # Number of load instructions
system.cpu0.num_store_insts 71579439 # Number of store instructions
system.cpu0.num_idle_cycles 493874204.516617 # Number of idle cycles
system.cpu0.num_busy_cycles 12021712.483383 # Number of busy cycles
system.cpu0.not_idle_fraction 0.023763 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.976237 # Percentage of idle cycles
system.cpu0.Branches 93830955 # Number of branches fetched
system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu 343614791 69.43% 69.43% # Class of executed instruction
system.cpu0.op_class::IntMult 1086596 0.22% 69.65% # Class of executed instruction
system.cpu0.op_class::IntDiv 48369 0.01% 69.66% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.66% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 49130 0.01% 69.67% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction
system.cpu0.op_class::MemRead 78499668 15.86% 85.54% # Class of executed instruction
system.cpu0.op_class::MemWrite 71579439 14.46% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 494878036 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 16312 # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements 10193982 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999718 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 304221340 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 10194494 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 29.841730 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.636821 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 5.388351 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 10.974546 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968041 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.010524 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.021435 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 204 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 1293146150 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1293146150 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 73192810 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 24078178 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 59062839 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 156333827 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 67632120 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 22097804 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 49843167 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 139573091 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 193481 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58228 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 144072 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 395781 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 150752 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data 54007 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu2.data 125506 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 330265 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1823556 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 547758 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 1229270 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 3600584 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1933646 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 595016 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 1413472 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 3942134 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 140824930 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 46175982 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 108906006 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 295906918 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 141018411 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 46234210 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 109050078 # number of overall hits
system.cpu0.dcache.overall_hits::total 296302699 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 2530012 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 810343 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 4548856 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 7889211 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1084459 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 324852 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 4363130 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 5772441 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 629295 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 177552 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 467332 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 1274179 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 753152 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data 142541 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu2.data 338665 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 1234358 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 110926 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 47584 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 233520 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 392030 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 7 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 3614471 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 1135195 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 8911986 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 13661652 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 4243766 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 1312747 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 9379318 # number of overall misses
system.cpu0.dcache.overall_misses::total 14935831 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 12443944000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 69833838000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 82277782000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9722892000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 137997538214 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 147720430214 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 3829880000 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 11756491801 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 15586371801 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 699957500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 2904634000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 3604591500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 164000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 111000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 275000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 22166836000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 207831376214 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 229998212214 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 22166836000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 207831376214 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 229998212214 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 75722822 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 24888521 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 63611695 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 164223038 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 68716579 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 22422656 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 54206297 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 145345532 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 822776 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 235780 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 611404 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1669960 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 903904 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 196548 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 464171 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1564623 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1934482 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 595342 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 1462790 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 3992614 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1933646 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 595018 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 1413479 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 3942143 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 144439401 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 47311177 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 117817992 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 309568570 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 145262177 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 47546957 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 118429396 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 311238530 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033411 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032559 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.071510 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.048040 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015782 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014488 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.080491 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.039715 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764844 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.753041 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.764359 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.763000 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.833221 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.725222 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.729613 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788917 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.057341 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.079927 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.159640 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.098189 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000003 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000005 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025024 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023994 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.075642 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.044131 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029215 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027609 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.079198 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.047988 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15356.391059 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15351.956184 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10429.152167 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29930.220531 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31628.106019 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 25590.634918 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 26868.620257 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 34714.221431 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 12627.108020 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14709.934011 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 12438.480644 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9194.682805 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 82000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 15857.142857 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 30555.555556 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19526.897141 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23320.433427 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16835.314808 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16885.840150 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22158.474232 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 15399.090430 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 17007920 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 25831 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 1141319 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 442 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.901986 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 58.441176 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 7849789 # number of writebacks
system.cpu0.dcache.writebacks::total 7849789 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 2357 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 2525238 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 2527595 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1733 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 3623036 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 3624769 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 2374 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 2374 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 10549 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 144753 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 155302 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 4090 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 6148274 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 6152364 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 4090 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 6148274 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 6152364 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 807986 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 2023618 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 2831604 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 323119 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 740094 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1063213 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 177438 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 455361 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 632799 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 142541 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 336291 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 478832 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 37035 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 88767 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125802 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 2 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 7 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 1131105 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 2763712 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 3894817 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 1308543 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 3219073 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 4527616 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 4998 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 8152 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 13150 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 4942 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 7788 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 12730 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 9940 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 15940 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 25880 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 11585855500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 31062083000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42647938500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9355442500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 24215406665 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33570849165 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2741056000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 8202281000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10943337000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 3687339000 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 11324765301 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 15012104301 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 496140000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 1176567000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1672707000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 162000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 104000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 266000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 20941298000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 55277489665 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 76218787665 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 23682354000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 63479770665 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 87162124665 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 826187000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1474974000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2301161000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 827724000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1436870963 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2264594963 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1653911000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2911844963 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4565755963 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032464 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031812 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014410 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013653 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007315 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.752557 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.744779 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.378931 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.725222 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.724498 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.306037 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062208 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.060683 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.031509 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000005 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023908 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023457 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.012581 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027521 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027181 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14339.178525 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15349.775995 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15061.406362 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28953.551168 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32719.366276 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31574.904713 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15447.964923 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 18012.699814 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17293.543447 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 25868.620257 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 33675.493251 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31351.505958 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13396.516808 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13254.554057 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13296.346640 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14857.142857 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 29555.555556 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18514.017708 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20001.175833 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19569.285968 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18098.261960 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19719.891616 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19251.218448 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165303.521409 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 180934.003925 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174993.231939 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167487.656819 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 184498.069209 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177894.341163 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 166389.436620 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 182675.342723 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176420.245866 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 14504187 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.976820 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 610702941 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 14504699 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 42.103800 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 9090101500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 497.013968 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 4.629060 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.333792 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.970730 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.009041 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020183 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 640161996 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 640161996 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 414014521 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 133530266 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 63158154 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 610702941 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 414014521 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 133530266 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 63158154 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 610702941 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 414014521 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 133530266 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 63158154 # number of overall hits
system.cpu0.icache.overall_hits::total 610702941 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 6587154 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 2095893 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 6271180 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 14954227 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 6587154 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 2095893 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 6271180 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 14954227 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 6587154 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 2095893 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 6271180 # number of overall misses
system.cpu0.icache.overall_misses::total 14954227 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 28071619000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 82050168313 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 110121787313 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 28071619000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 82050168313 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 110121787313 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 28071619000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 82050168313 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 110121787313 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 420601675 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 135626159 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 69429334 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 625657168 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.demand_accesses::cpu1.inst 135626159 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 69429334 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 625657168 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 420601675 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 135626159 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 69429334 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 625657168 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015661 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015453 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.090325 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.023902 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015661 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015453 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.090325 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.023902 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015661 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015453 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.090325 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.023902 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13393.631736 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13083.688925 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 7363.923746 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13393.631736 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13083.688925 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 7363.923746 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13393.631736 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13083.688925 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 7363.923746 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 53098 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 4092 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.976051 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 449399 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 449399 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 449399 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 449399 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 449399 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 449399 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 2095893 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 5821781 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 7917674 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 2095893 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 5821781 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 7917674 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 2095893 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 5821781 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 7917674 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 25975726000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 72655138349 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 98630864349 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 25975726000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 72655138349 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 98630864349 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 25975726000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 72655138349 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 98630864349 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015453 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.083852 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012655 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015453 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.083852 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.012655 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015453 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.083852 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.012655 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12393.631736 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12479.881732 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12457.050435 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12393.631736 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12479.881732 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12457.050435 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12393.631736 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12479.881732 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12457.050435 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 40125 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 40125 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6166 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 29054 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 2 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 40123 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 0.299080 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 59.907962 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-1023 40122 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 40123 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 35222 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 25010.164102 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 22134.109650 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 13083.481555 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767 22653 64.31% 64.31% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535 12324 34.99% 99.30% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303 130 0.37% 99.67% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071 82 0.23% 99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607 11 0.03% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375 3 0.01% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143 6 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911 7 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 35222 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples -2750429288 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 1.373730 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1027918000 -37.37% -37.37% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 -3778347288 137.37% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -2750429288 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 29054 82.49% 82.49% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 6166 17.51% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 35220 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 40125 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 40125 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 35220 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 35220 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 75345 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 25724641 # DTB read hits
system.cpu1.dtb.read_misses 30962 # DTB read misses
system.cpu1.dtb.write_hits 23221976 # DTB write hits
system.cpu1.dtb.write_misses 9163 # DTB write misses
system.cpu1.dtb.flush_tlb 1277 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 6096 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 163 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 21958 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 1268 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 2784 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 25755603 # DTB read accesses
system.cpu1.dtb.write_accesses 23231139 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 48946617 # DTB hits
system.cpu1.dtb.misses 40125 # DTB misses
system.cpu1.dtb.accesses 48986742 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 23205 # Table walker walks requested
system.cpu1.itb.walker.walksLong 23205 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1161 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 20405 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 23205 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 23205 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 23205 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 21566 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 27973.105815 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 25131.407006 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 15236.984733 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767 11031 51.15% 51.15% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535 10248 47.52% 98.67% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303 108 0.50% 99.17% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071 142 0.66% 99.83% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607 12 0.06% 99.89% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375 2 0.01% 99.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143 10 0.05% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911 2 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679 6 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 21566 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 20405 94.62% 94.62% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 1161 5.38% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 21566 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 23205 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 23205 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 21566 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 21566 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 44771 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 135626159 # ITB inst hits
system.cpu1.itb.inst_misses 23205 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 1277 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 6096 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 163 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 16107 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 135649364 # ITB inst accesses
system.cpu1.itb.hits 135626159 # DTB hits
system.cpu1.itb.misses 23205 # DTB misses
system.cpu1.itb.accesses 135649364 # DTB accesses
system.cpu1.numCycles 1276121974 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 135538016 # Number of instructions committed
system.cpu1.committedOps 159130731 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 146160247 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 138681 # Number of float alu accesses
system.cpu1.num_func_calls 7978033 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 20702063 # number of instructions that are conditional controls
system.cpu1.num_int_insts 146160247 # number of integer instructions
system.cpu1.num_fp_insts 138681 # number of float instructions
system.cpu1.num_int_register_reads 211618661 # number of times the integer registers were read
system.cpu1.num_int_register_writes 115744147 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 219623 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 127108 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 35291781 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 35222922 # number of times the CC registers were written
system.cpu1.num_mem_refs 48943439 # number of memory refs
system.cpu1.num_load_insts 25723579 # Number of load instructions
system.cpu1.num_store_insts 23219860 # Number of store instructions
system.cpu1.num_idle_cycles 1249309266.868014 # Number of idle cycles
system.cpu1.num_busy_cycles 26812707.131986 # Number of busy cycles
system.cpu1.not_idle_fraction 0.021011 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.978989 # Percentage of idle cycles
system.cpu1.Branches 30260595 # Number of branches fetched
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu 109906813 69.03% 69.03% # Class of executed instruction
system.cpu1.op_class::IntMult 333855 0.21% 69.24% # Class of executed instruction
system.cpu1.op_class::IntDiv 14527 0.01% 69.25% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.25% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 20240 0.01% 69.26% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.26% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.26% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.26% # Class of executed instruction
system.cpu1.op_class::MemRead 25723579 16.16% 85.42% # Class of executed instruction
system.cpu1.op_class::MemWrite 23219860 14.58% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 159218874 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.branchPred.lookups 96379868 # Number of BP lookups
system.cpu2.branchPred.condPredicted 65507682 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 4329047 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 66096416 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 46823178 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 70.840722 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 12400698 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 133614 # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.dtb.walker.walks 662632 # Table walker walks requested
system.cpu2.dtb.walker.walksLong 662632 # Table walker walks initiated with long descriptors
system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 11252 # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 67139 # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walksSquashedBefore 410741 # Table walks squashed before starting
system.cpu2.dtb.walker.walkWaitTime::samples 251891 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::mean 2203.738919 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::stdev 12798.903480 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0-65535 250391 99.40% 99.40% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::65536-131071 1085 0.43% 99.84% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::131072-196607 243 0.10% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::196608-262143 75 0.03% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::262144-327679 48 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::327680-393215 26 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::393216-458751 21 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total 251891 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples 304707 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 22494.824536 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 18425.462627 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev 15718.326432 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-65535 298255 97.88% 97.88% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::65536-131071 5951 1.95% 99.84% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::131072-196607 243 0.08% 99.92% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::196608-262143 191 0.06% 99.98% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::262144-327679 38 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::327680-393215 19 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total 304707 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples 640151154620 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::mean 0.510260 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::stdev 0.628480 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0-3 639427998620 99.89% 99.89% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::4-7 404049000 0.06% 99.95% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::8-11 134377500 0.02% 99.97% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::12-15 87391000 0.01% 99.98% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::16-19 34713500 0.01% 99.99% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::20-23 17695000 0.00% 99.99% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::24-27 17014000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::28-31 22612000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::32-35 4758500 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::36-39 448500 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::40-43 50500 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::44-47 27500 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::48-51 19000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total 640151154620 # Table walker pending requests distribution
system.cpu2.dtb.walker.walkPageSizes::4K 67139 85.65% 85.65% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::2M 11252 14.35% 100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total 78391 # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 662632 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 662632 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 78391 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 78391 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total 741023 # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
system.cpu2.dtb.read_hits 76683824 # DTB read hits
system.cpu2.dtb.read_misses 455088 # DTB read misses
system.cpu2.dtb.write_hits 59509350 # DTB write hits
system.cpu2.dtb.write_misses 207544 # DTB write misses
system.cpu2.dtb.flush_tlb 1276 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 14760 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 390 # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries 38772 # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 82 # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults 6499 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults 41159 # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 77138912 # DTB read accesses
system.cpu2.dtb.write_accesses 59716894 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
system.cpu2.dtb.hits 136193174 # DTB hits
system.cpu2.dtb.misses 662632 # DTB misses
system.cpu2.dtb.accesses 136855806 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.itb.walker.walks 81585 # Table walker walks requested
system.cpu2.itb.walker.walksLong 81585 # Table walker walks initiated with long descriptors
system.cpu2.itb.walker.walksLongTerminationLevel::Level2 2498 # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walksLongTerminationLevel::Level3 56536 # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walksSquashedBefore 10896 # Table walks squashed before starting
system.cpu2.itb.walker.walkWaitTime::samples 70689 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::mean 1473.991710 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::stdev 8586.891139 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0-32767 70027 99.06% 99.06% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::32768-65535 428 0.61% 99.67% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::65536-98303 144 0.20% 99.87% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::98304-131071 50 0.07% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::131072-163839 13 0.02% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::294912-327679 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total 70689 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples 69930 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 28234.749035 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 24509.520790 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev 16350.855698 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::0-32767 36490 52.18% 52.18% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::32768-65535 32158 45.99% 98.17% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::65536-98303 628 0.90% 99.06% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::98304-131071 491 0.70% 99.77% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::131072-163839 45 0.06% 99.83% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::163840-196607 57 0.08% 99.91% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::196608-229375 23 0.03% 99.95% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::229376-262143 10 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::262144-294911 12 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::360448-393215 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total 69930 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples 485530683964 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::mean 0.892648 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::stdev 0.309939 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0 52174022580 10.75% 10.75% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::1 433310679884 89.24% 99.99% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::2 41019000 0.01% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::3 4632000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::4 311000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::5 12000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::6 6000 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::7 1500 0.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total 485530683964 # Table walker pending requests distribution
system.cpu2.itb.walker.walkPageSizes::4K 56536 95.77% 95.77% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::2M 2498 4.23% 100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total 59034 # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 81585 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total 81585 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 59034 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total 59034 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total 140619 # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits 69601857 # ITB inst hits
system.cpu2.itb.inst_misses 81585 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.flush_tlb 1276 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 14760 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 390 # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries 30530 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults 148496 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.inst_accesses 69683442 # ITB inst accesses
system.cpu2.itb.hits 69601857 # DTB hits
system.cpu2.itb.misses 81585 # DTB misses
system.cpu2.itb.accesses 69683442 # DTB accesses
system.cpu2.numCycles 461100419 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 177123206 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 428437277 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 96379868 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 59223876 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 257401667 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 9762973 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 2005280 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles 7949 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 2437 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 3773015 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 114784 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 5106 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 69429398 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 2656278 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes 32686 # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples 445314772 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.124877 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.366658 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 339836575 76.31% 76.31% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 13185142 2.96% 79.27% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 13574991 3.05% 82.32% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 9797674 2.20% 84.52% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 20004635 4.49% 89.02% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 6578482 1.48% 90.49% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 7061868 1.59% 92.08% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 6288982 1.41% 93.49% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 28986423 6.51% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 445314772 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.209021 # Number of branch fetches per cycle
system.cpu2.fetch.rate 0.929163 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 144945569 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 209061419 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 78115064 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 9308814 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 3881927 # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved 14332703 # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred 1014310 # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts 468249315 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 3113109 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 3881927 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 150342023 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 16281945 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 167363518 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 81901775 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 25541188 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 457027313 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 55411 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 1577150 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 1077305 # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents 12432724 # Number of times rename has blocked due to SQ full
system.cpu2.rename.FullRegisterEvents 2850 # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands 436738370 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 696876474 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 538877799 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 611175 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 365603185 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 71135185 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 10148334 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 8698822 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 51282276 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 73817911 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 62641049 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 9297155 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 10241835 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 434108561 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 10116895 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 433413553 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 631683 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 59503474 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 37916216 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 236413 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 445314772 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 0.973275 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.689353 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 278168249 62.47% 62.47% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 68048730 15.28% 77.75% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 31692331 7.12% 84.86% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 22597394 5.07% 89.94% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 16978227 3.81% 93.75% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 11874624 2.67% 96.42% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 7985798 1.79% 98.21% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 4768189 1.07% 99.28% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 3201230 0.72% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 445314772 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 2163580 25.08% 25.08% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 17452 0.20% 25.29% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 1463 0.02% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.30% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 3490107 40.46% 65.77% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 2952914 34.23% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 293684501 67.76% 67.76% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 1025227 0.24% 68.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 47766 0.01% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 317 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 1 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.01% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 48576 0.01% 68.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 68.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.02% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.02% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 78271434 18.06% 86.08% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 60335731 13.92% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 433413553 # Type of FU issued
system.cpu2.iq.rate 0.939955 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 8625516 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.019901 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 1320585789 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 503812289 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 417285848 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 813288 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 405263 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 361974 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 441604210 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 434859 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 3381259 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 11998288 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 16552 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 496769 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 6557326 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 2684885 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 5754188 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 3881927 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 10679636 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 4407291 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 444323917 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 1337797 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 73817911 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 62641049 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 8508217 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 157244 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 4192594 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 496769 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 2009659 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 1725096 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 3734755 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 428275662 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 76671253 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 4484086 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 98461 # number of nop insts executed
system.cpu2.iew.exec_refs 136179692 # number of memory reference insts executed
system.cpu2.iew.exec_branches 79539500 # Number of branches executed
system.cpu2.iew.exec_stores 59508439 # Number of stores executed
system.cpu2.iew.exec_rate 0.928812 # Inst execution rate
system.cpu2.iew.wb_sent 418566552 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 417647822 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 206637380 # num instructions producing a value
system.cpu2.iew.wb_consumers 358874398 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 0.905763 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.575793 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 59540982 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 9880482 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 3329329 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 435241532 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 0.883928 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.881300 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 296713491 68.17% 68.17% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 66287598 15.23% 83.40% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 24183303 5.56% 88.96% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 11166549 2.57% 91.52% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 8012002 1.84% 93.36% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 4870056 1.12% 94.48% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 4489994 1.03% 95.52% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 2918433 0.67% 96.19% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 16600106 3.81% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 435241532 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 327785464 # Number of instructions committed
system.cpu2.commit.committedOps 384721982 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 117903346 # Number of memory references committed
system.cpu2.commit.loads 61819623 # Number of loads committed
system.cpu2.commit.membars 2573370 # Number of memory barriers committed
system.cpu2.commit.branches 73211237 # Number of branches committed
system.cpu2.commit.fp_insts 346819 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 353394375 # Number of committed integer instructions.
system.cpu2.commit.function_calls 9534563 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu 265954850 69.13% 69.13% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult 786882 0.20% 69.33% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 35653 0.01% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.34% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc 41251 0.01% 69.35% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.35% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.35% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.35% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead 61819623 16.07% 85.42% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite 56083723 14.58% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total 384721982 # Class of committed instruction
system.cpu2.commit.bw_lim_events 16600106 # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads 860271406 # The number of ROB reads
system.cpu2.rob.rob_writes 898612976 # The number of ROB writes
system.cpu2.timesIdled 2954119 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 15785647 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 99456385277 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 327785464 # Number of Instructions Simulated
system.cpu2.committedOps 384721982 # Number of Ops (including micro ops) Simulated
system.cpu2.cpi 1.406714 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.406714 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.710877 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.710877 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 503674657 # number of integer regfile reads
system.cpu2.int_regfile_writes 298593848 # number of integer regfile writes
system.cpu2.fp_regfile_reads 690106 # number of floating regfile reads
system.cpu2.fp_regfile_writes 421944 # number of floating regfile writes
system.cpu2.cc_regfile_reads 91580916 # number of cc regfile reads
system.cpu2.cc_regfile_writes 92419773 # number of cc regfile writes
system.cpu2.misc_regfile_reads 837090025 # number of misc regfile reads
system.cpu2.misc_regfile_writes 9982057 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 40263 # Transaction distribution
system.iobus.trans_dist::ReadResp 40263 # Transaction distribution
system.iobus.trans_dist::WriteReq 136537 # Transaction distribution
system.iobus.trans_dist::WriteResp 136537 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47686 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122568 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47706 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155698 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7492024 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 13118000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 7299000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 33000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 16991000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 175678218 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 37744000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 35540000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 80000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 115457 # number of replacements
system.iocache.tags.tagsinuse 10.416552 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 13085993128009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 5.913060 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 4.503492 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.369566 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.281468 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651035 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039641 # Number of tag accesses
system.iocache.tags.data_accesses 1039641 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses
system.iocache.demand_misses::total 8852 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 8812 # number of overall misses
system.iocache.overall_misses::total 8852 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 2432000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 80359879 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 82791879 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 3987954339 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 3987954339 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 2432000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 80359879 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 82791879 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 2432000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 80359879 # number of overall miss cycles
system.iocache.overall_miss_latency::total 82791879 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 65729.729730 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 9119.368929 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 9356.071760 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 37388.006628 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 37388.006628 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 60800 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 9119.368929 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 9352.900926 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 60800 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 9119.368929 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 9352.900926 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 1026 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 106 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 9.679245 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 16 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 518 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 534 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 33736 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 33736 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 16 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide 518 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 534 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 16 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 518 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 534 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 1632000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 54459879 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 56091879 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2301154339 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2301154339 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 1632000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 54459879 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 56091879 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 1632000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 54459879 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 56091879 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 0.432432 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.058783 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.060346 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.316283 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.316283 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 0.058783 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.060325 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 0.058783 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.060325 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102000 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 105134.901544 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 105040.971910 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68210.645571 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68210.645571 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 102000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 105134.901544 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 105040.971910 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 102000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 105134.901544 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 105040.971910 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 1303829 # number of replacements
system.l2c.tags.tagsinuse 65263.667418 # Cycle average of tags in use
system.l2c.tags.total_refs 45613639 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1366689 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 33.375288 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 37041.292991 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 185.441819 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 257.864893 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3799.344283 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 8420.169172 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 49.795293 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 72.886191 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 899.312109 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2654.836821 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 113.517705 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker 173.967622 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 2205.940609 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 9389.297910 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.565205 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002830 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.003935 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.057973 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.128482 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000760 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.001112 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.013722 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.040510 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.001732 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker 0.002655 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.033660 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.143269 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.995845 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 366 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 62494 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 365 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 561 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2733 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 4954 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 54104 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.005585 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.953583 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 407870689 # Number of tag accesses
system.l2c.tags.data_accesses 407870689 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 197247 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 127080 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 74241 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 49038 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 389886 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 153027 # number of ReadReq hits
system.l2c.ReadReq_hits::total 990519 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 7849789 # number of Writeback hits
system.l2c.Writeback_hits::total 7849789 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 4877 # number of UpgradeReq hits
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system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.213975 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.081595 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.008097 # mshr miss rate for demand accesses
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system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 96667.166959 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 89004.675500 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77405.115512 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78004.480287 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71136.002761 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71119.602810 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77750.839490 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 79603.039288 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 75587.758611 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 86673.366680 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 81333.087693 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77405.115512 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78004.480287 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71136.002761 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71119.602810 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77750.839490 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 79603.039288 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 75587.758611 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 86673.366680 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 81333.087693 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152803.521409 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 168434.003925 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 162493.231939 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 155987.656819 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 172992.937853 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 166391.201885 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 154386.619718 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 170661.417817 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 164410.587326 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 76733 # Transaction distribution
system.membus.trans_dist::ReadResp 468089 # Transaction distribution
system.membus.trans_dist::WriteReq 33644 # Transaction distribution
system.membus.trans_dist::WriteResp 33644 # Transaction distribution
system.membus.trans_dist::Writeback 1209847 # Transaction distribution
system.membus.trans_dist::CleanEvict 210029 # Transaction distribution
system.membus.trans_dist::UpgradeReq 36410 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 36413 # Transaction distribution
system.membus.trans_dist::ReadExReq 1013774 # Transaction distribution
system.membus.trans_dist::ReadExResp 1013774 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 391356 # Transaction distribution
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122568 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6750 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4261294 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4390673 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 345792 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 345792 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4736465 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155698 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13500 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 160146208 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 160315602 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7368448 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7368448 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 167684050 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 579 # Total snoops (count)
system.membus.snoop_fanout::samples 3078821 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 3078821 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 3078821 # Request fanout histogram
system.membus.reqLayer0.occupancy 45758500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 2500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 1294500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 3125844189 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 2930708426 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 61033927 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.trans_dist::ReadReq 1510117 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 22871416 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33644 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 33644 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 8317119 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 16946911 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 45584 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 45593 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 2106266 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 2106266 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 14504828 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 6856794 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 1265720 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 1231984 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 43598497 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30808593 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 852484 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1760318 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 77019892 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 928472660 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1076191614 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3123312 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6312032 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 2014099618 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 938060 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 51670008 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.040962 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.198203 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 49553478 95.90% 95.90% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 2116530 4.10% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 51670008 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 17416968994 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 316500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 11880834300 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 7217033015 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 275805669 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 649517949 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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