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17 commits

Author SHA1 Message Date
Jason Lowe-Power
7520331402 tests: Regression stats updated for recent patches 2016-11-30 17:12:59 -05:00
Andreas Hansson
607c277291 stats: Update stats to reflect recent changes to floats 
Mostly just splitting out the floats ops and corresponding
reads/writes.
 2016-10-19 06:20:04 -04:00
Curtis Dunham
c87b717dbd stats: update references 2016-10-13 23:21:40 +01:00
Andreas Sandberg
55ed9609f1 stats: Update to match classic memory changes 2016-08-12 14:12:59 +01:00
Curtis Dunham
84f138ba96 stats: update references 2016-07-21 17:19:18 +01:00
Andreas Sandberg
85997e66a0 stats: Add power stats to test references 
Change-Id: Ic827213134b199446822f128b81d4a480e777fee
 2016-06-06 17:16:44 +01:00
Curtis Dunham
62b6ff22ec stats: update for snoop filter tweak 
--HG--
extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
 2016-05-31 11:07:18 +01:00
Andreas Hansson
b006ad26d4 stats: Update stats to reflect cache changes 
Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.
 2016-04-21 04:48:24 -04:00
Curtis Dunham
1d61224a8b stats: update stats for thermals, indirect BP 2016-04-08 11:01:45 -05:00
Steve Reinhardt
d7c083864c stats: update stats for ld.so support 
Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
 2016-03-17 10:32:53 -07:00
Steve Reinhardt
9d8fec0d90 stats: update stats for mmap() change. 
SE O3 runs see an additional reg read per mmap() call.
 2016-03-17 10:25:11 -07:00
Tony Gutierrez
1285d639eb stats: update stats to after GPU checkin 2016-01-22 10:42:13 -05:00
Anthony Gutierrez
4935f0d5ff stats: bump stats to reflect ruby tester changes 2015-12-12 17:27:38 -05:00
Nilay Vaish
de489e1997 stats: updates due to recent chagnesets 2015-11-16 05:08:57 -06:00
Nilay Vaish
e1385784f2 stats: remove wb_penalized and wb_penalized_rate 2015-11-16 04:58:29 -06:00
Andreas Hansson
324bc9771d stats: Update stats to match cache changes 2015-11-06 03:26:50 -05:00
Andreas Sandberg
17dbb49294 tests: Update SMT tests to correctly configure CPUs 
The 01.hello-2T-smt test case for the O3 CPU didn't correctly setup
the number of threads before creating interrupt controllers, which
confused the constructor in BaseCPU. This changeset adds SMT support
to the test configuration infrastructure.

--HG--
rename : tests/configs/o3-timing.py => tests/configs/o3-timing-mt.py
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
rename : tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
 2015-10-05 13:13:23 -05:00