it makes more sense and is less confusing.
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
width is a better name than multiplier
--HG--
extra : convert_revision : ea2fa4faa160f5657aece41df469bbc9f7244b21
sim/main.cc:
For some unknown reason linux's basename doesn't take a const char *
--HG--
extra : convert_revision : 30289195881e16a05429f7025abab7914a9e3eb6
configuration so that we can always have binning on.
base/statistics.cc:
If we're binning, and there is no bin active at the time
we check all stats stuff, create a bin.
base/statistics.hh:
FS_MEASURE doesn't exist anymore
base/stats/text.cc:
don't print out bin names if there is only one bin
sim/process.cc:
don't zero stats. It happens automatically.
Don't activate the context at the time it is registered,
instead activate the first context in a startup callback.
sim/process.hh:
Add startup callback to initialize the first exec context
--HG--
extra : convert_revision : bcb23cdb184b0abf7cecd79902f8a59b50f71fe4
outside of the loop so we get all of the jobs, not just the
last one.
util/pbs/send.py:
fix indent
--HG--
extra : convert_revision : eee9546b4945ff949fdfdf339fc95a23603b47d3
add dprintf on alignment faults
fix RR benchmark rcS script name
Add Dual test without rcS script
Update Monet to be closer to the real thing
Fix p4/monet configs
Add a way to read the DRIR register with at 32bit access for validation
SConscript:
build/SConstruct:
always use mysql if the libraries are installed
arch/alpha/alpha_memory.cc:
Add a DPRINTF to print alignment faults when they happen
dev/tsunami_cchip.cc:
Add a way to read the DRIR for validation.
--HG--
extra : convert_revision : 8c112c958f36b785390c46e70a889a79c6bea015
output files and the output directory are are handled. Make
the output directory configuration via a command line parameter,
or an environment variable.
SConscript:
Add new output file stuff
base/misc.cc:
dev/simconsole.cc:
use new output file code
cpu/base_cpu.cc:
use new output file code to generate output streams
dev/etherdump.cc:
use the output file code to find the output directory
use a real stream instead of a pointer
dev/etherdump.hh:
use a real stream instead of a pointer
objects/Root.mpy:
output_dir and config_output_file are not longer configured here.
sim/main.cc:
- Completely rework the command line argument passing to deal with
changes in python and output files.
- Update help output to reflect changes.
- Remove all direct support for .ini files. They are strictly
for intermediate representation.
- Remove the --foo:bar=blah syntax for .ini files and add --foo.bar=blah
syntax for python. This will generate: foo.bar = 'blah' in the python
script.
- Add '-d' to set the output directory.
- Use new output file code to access the output stream.
sim/serialize.cc:
use the new code to find the output directory
sim/universe.cc:
Get rid of makeOutputStream. Use the new output file code.
Remove output_dir and config_output_file as parameters.
--HG--
extra : convert_revision : df2f0e13d401c3a60cae1239aa1ec3511721544d
sim/pyconfig/m5config.py:
When getting all values, make sure we get the ones that are
parameter defaults as well.
--HG--
extra : convert_revision : 2b1c4b2f27dfab17ef9df18d7e5936e4a00bb12e
sim/pyconfig/SConscript:
Embed the jobfile.py script into the binary so that we don't
need to copy it into the Base directory every time.
test/genini.py:
Add the util/pbs directory to the path so we can get to
jobfile.py
Add a -I argument to set to add to the path.
util/pbs/pbs.py:
Create a MyPOpen class. This is a lot like the popen2.Popen3 class
in the python library except that my version allows redirection of
standard in and standard out to a file instead of a pipe.
Use this popen class to execute qsub or ssh qsub. This was important
for the ssh version of qsub because we need to pipe the script into
standard in of ssh so that the script can get to the qsub command.
(Otherwise we have a problem discovering the path.)
util/pbs/send.py:
Tweak the script so it figures out paths in NFS correctly.
Use the new system for running qsub.
--HG--
extra : convert_revision : 1289915ba99cec6fd464b71215c32d2197ff2824
objects/Root.mpy:
Fake the param context stuff for now.
sim/param.cc:
Make empty vector enums work
sim/serialize.cc:
serialize_dir is always valid
--HG--
extra : convert_revision : c46373f0f4c70e6a2f01a81c0fa6bacab72d4c4f
util/pbs/send.py:
- add a -d to set the job root directory allowing one to run
send.py from anywhere.
- specify full paths to files instead of relative paths to make -d
work and to allow ssh qsub to work again.
- make the Link directory only copy links that point to regular files.
--HG--
extra : convert_revision : dd330cee08b97c5d72c3d58ef123f83ac7ccede7
base/str.cc:
base/str.hh:
Add a couple functions that allow you to split a string at
the first or last instance of a delimiter.
--HG--
extra : convert_revision : 2af22639e1b67ac61577c00475a555841a56f902
Increase the default number of CSHR's, we should really fix this or make it a parameter
Use a setBlocked call to tell the bus it should block
New technique for sampling and switchover:
1) Sampler switchover event happens
2) All cpus in the current phase of sampling associated with this sampler are signaled to switchover
3) Each cpu drains it's pipe of things being executed (stops fetching and waits for empty pipe)
4) Once the pipe is empty the cpu calls back to the sampler to signal it has finished, and moves into the switchedout state (continues not to fetch)
5) The sampler collects all the signals, once all cpus are drained it calls the new cpu's in the next phase to takeover from the correct cpu
6) The statistics are reset and the next switchover time is calculated from this point
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
Reconfigure the way the sampling switchover works
cpu/pc_event.cc:
More debugging information on kernel panic's
kern/linux/linux_system.cc:
More debug info for Kernel Die events
kern/linux/linux_system.hh:
More debug info for kernel die events
--HG--
extra : convert_revision : 61cc42e43ba738705aa1f1d167b65d4d6dee51ae
Fix up configuration scrupts to have better support for
running on the simulation pool.
--HG--
extra : convert_revision : 0178c8600b193d6c0ca69163fb735a7fa0e70782
dev/tsunami_cchip.cc:
add a fake register to tsunami that we can do 32bit reads to.
Warn on access.
--HG--
extra : convert_revision : d87860f3b527528151c23431556039bca6e12945
util/tracediff:
Fix bug (used += instead of .= for string concatenation in Perl...
wrong language!).
Also updated for new config (s/Universe/root/).
--HG--
extra : convert_revision : 0db3f22794037dc51cc29f78a75bd22012a8ecd9
address calculation and memory access portions separately.
Not currently used by any CPU models, but Kevin says he needs this.
Also clean up handling of execution tracing for memory accesses
(move it all into isa_desc and out of CPU models).
Got rid of some ancient unused code too.
arch/alpha/isa_desc:
Add execute() methods to EAComp and MemAcc portions of memory
access instructions, to allow CPU models to execute the effective
address calculation and memory access portions separately.
Requires the execution context to remember the effective address
across the two invocations. Added setEA() and getEA() methods to
execution context to support this. A model that does not use the
split execution model can panic if these methods are called.
Also added hook to call traceData->setAddr() after EA computation
on any load or store operation.
arch/isa_parser.py:
Call traceData->setData() on memory writes (stores).
cpu/simple_cpu/simple_cpu.cc:
Get rid of unused code.
cpu/simple_cpu/simple_cpu.hh:
Add (non-functional) setEA() and getEA() methods for new
split memory access execution support.
--HG--
extra : convert_revision : bc2d2c758c4ca753812b9fa81f21038e55929ff0
get rid of the alias for true to True and false to False to keep
consistent python syntax.
util/stats/info.py:
Fix typo
--HG--
extra : convert_revision : e69588a8de52424e043315e70008ca3a3ede7d5b
dev/simconsole.cc:
sim/universe.cc:
isValid isn't compatible with new python stuff, so whack it.
--HG--
extra : convert_revision : 0c50038769a558650479c51122a8be5d92e7d9c4
objects/AlphaConsole.mpy:
objects/AlphaTLB.mpy:
objects/BadDevice.mpy:
objects/BaseCPU.mpy:
objects/BaseCache.mpy:
objects/BaseSystem.mpy:
objects/Bus.mpy:
objects/CoherenceProtocol.mpy:
objects/Device.mpy:
objects/DiskImage.mpy:
objects/Ethernet.mpy:
objects/Ide.mpy:
objects/IntrControl.mpy:
objects/MemTest.mpy:
objects/Pci.mpy:
objects/PhysicalMemory.mpy:
objects/Platform.mpy:
objects/Process.mpy:
objects/Repl.mpy:
objects/Root.mpy:
objects/SimConsole.mpy:
objects/SimpleDisk.mpy:
objects/Tsunami.mpy:
objects/Uart.mpy:
simobj now requires a type= line if it is actually intended
to be a type
sim/pyconfig/SConscript:
keep track of the filename of embedded files for better
error messages.
sim/pyconfig/m5config.py:
Add support for the trickery done with the compiler to get the
simobj language feature added to the importer.
fix the bug that gave objects the wrong name in error messages.
test/genini.py:
Globals have been fixed and use execfile
--HG--
extra : convert_revision : b74495fd6f3479a87ecea7f1234ebb6731279b2b
objects/BaseCache.mpy:
add all the Split parameters to the BaseCache simobj.
--HG--
extra : convert_revision : 4fcba3ce730f730ca8628ac7f4aa0fb9476474ab
all but tlaser_node.cc dependence on tlaserreg.h
dev/tsunami_io.cc:
dev/tsunamireg.h:
removed tlaserreg.h
--HG--
extra : convert_revision : 148a5d79530e5ed721a49279f684a48041deed2b
