Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/m5 --HG-- extra : convert_revision : aea0708fa6684e3203c03f17e8ae6ae87e893f04
This commit is contained in:
Steve Reinhardt
commit
6dd5509490
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@ -790,48 +790,14 @@ output header {{
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protected:
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/// Constructor
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MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass,
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StaticInstPtr<AlphaISA> _eaCompPtr,
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StaticInstPtr<AlphaISA> _memAccPtr)
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StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
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StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
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: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
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};
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/**
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* Base class for "fake" effective-address computation
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* instructions returnded by eaCompInst().
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*/
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class EACompBase : public AlphaStaticInst
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{
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public:
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/// Constructor
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EACompBase(MachInst machInst)
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: AlphaStaticInst("(eacomp)", machInst, IntAluOp)
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{
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}
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%(BasicExecDeclare)s
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};
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/**
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* Base class for "fake" memory-access instructions returnded by
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* memAccInst().
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*/
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class MemAccBase : public AlphaStaticInst
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{
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public:
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/// Constructor
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MemAccBase(MachInst machInst, OpClass __opClass)
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: AlphaStaticInst("(memacc)", machInst, __opClass)
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{
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}
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%(BasicExecDeclare)s
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};
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}};
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@ -850,21 +816,6 @@ output decoder {{
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}
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}};
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output exec {{
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Fault
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EACompBase::execute(%(CPU_exec_context)s *, Trace::InstRecord *)
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{
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panic("attempt to execute eacomp");
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}
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Fault
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MemAccBase::execute(%(CPU_exec_context)s *, Trace::InstRecord *)
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{
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panic("attempt to execute memacc");
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}
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}};
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def format LoadAddress(code) {{
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iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
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header_output = BasicDeclare.subst(iop)
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@ -885,21 +836,25 @@ def template LoadStoreDeclare {{
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/**
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* "Fake" effective address computation class for "%(mnemonic)s".
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*/
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class EAComp : public EACompBase
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class EAComp : public %(base_class)s
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{
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public:
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/// Constructor
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EAComp(MachInst machInst);
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%(BasicExecDeclare)s
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};
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/**
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* "Fake" memory access instruction class for "%(mnemonic)s".
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*/
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class MemAcc : public MemAccBase
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class MemAcc : public %(base_class)s
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{
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public:
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/// Constructor
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MemAcc(MachInst machInst);
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%(BasicExecDeclare)s
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};
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public:
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@ -912,14 +867,17 @@ def template LoadStoreDeclare {{
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}};
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def template LoadStoreConstructor {{
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/** TODO: change op_class to AddrGenOp or something (requires
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* creating new member of OpClass enum in op_class.hh, updating
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* config files, etc.). */
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inline %(class_name)s::EAComp::EAComp(MachInst machInst)
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: EACompBase(machInst)
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: %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
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{
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%(ea_constructor)s;
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}
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inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
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: MemAccBase(machInst, %(op_class)s)
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: %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
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{
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%(memacc_constructor)s;
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}
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@ -932,6 +890,64 @@ def template LoadStoreConstructor {{
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}
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}};
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def template EACompExecute {{
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Fault
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%(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData)
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{
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Addr EA;
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Fault fault = No_Fault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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if (fault == No_Fault) {
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%(op_wb)s;
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xc->setEA(EA);
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}
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return fault;
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}
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}};
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def template MemAccExecute {{
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Fault
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%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData)
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{
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Addr EA;
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Fault fault = No_Fault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_nonmem_rd)s;
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EA = xc->getEA();
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if (fault == No_Fault) {
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%(op_mem_rd)s;
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%(code)s;
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}
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if (fault == No_Fault) {
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%(op_mem_wb)s;
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}
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if (fault == No_Fault) {
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%(postacc_code)s;
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}
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if (fault == No_Fault) {
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%(op_nonmem_wb)s;
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}
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return fault;
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}
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}};
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def template LoadStoreExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData)
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@ -1022,18 +1038,33 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
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# Would be nice to autogenerate this list, but oh well.
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valid_mem_flags = ['LOCKED', 'NO_FAULT', 'EVICT_NEXT', 'PF_EXCLUSIVE']
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inst_flags = []
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mem_flags = []
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for f in flags:
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if f in valid_mem_flags:
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mem_flags.append(f)
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else:
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inst_flags.append(f)
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mem_flags = [f for f in flags if f in valid_mem_flags]
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inst_flags = [f for f in flags if f not in valid_mem_flags]
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# add hook to get effective addresses into execution trace output.
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ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
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# generate code block objects
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ea_cblk = CodeBlock(ea_code)
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memacc_cblk = CodeBlock(memacc_code)
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postacc_cblk = CodeBlock(postacc_code)
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# Some CPU models execute the memory operation as an atomic unit,
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# while others want to separate them into an effective address
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# computation and a memory access operation. As a result, we need
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# to generate three StaticInst objects. Note that the latter two
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# are nested inside the larger "atomic" one.
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# generate InstObjParams for EAComp object
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ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
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# generate InstObjParams for MemAcc object
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memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
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# in the split execution model, the MemAcc portion is responsible
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# for the post-access code.
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memacc_iop.postacc_code = postacc_cblk.code
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# generate InstObjParams for unified execution
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cblk = CodeBlock(ea_code + memacc_code + postacc_code)
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iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
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@ -1043,13 +1074,17 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
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iop.memacc_code = memacc_cblk.code
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iop.postacc_code = postacc_cblk.code
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mem_flags = string.join(mem_flags, '|')
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if mem_flags != '':
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iop.constructor += '\n\tmemAccessFlags = ' + mem_flags + ';'
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if mem_flags:
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s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
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iop.constructor += s
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memacc_iop.constructor += s
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# (header_output, decoder_output, decode_block, exec_output)
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return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
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decode_template.subst(iop), exec_template.subst(iop))
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decode_template.subst(iop),
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EACompExecute.subst(ea_iop)
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+ MemAccExecute.subst(memacc_iop)
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+ exec_template.subst(iop))
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}};
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@ -1460,8 +1495,8 @@ output header {{
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/// Constructor
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HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass,
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StaticInstPtr<AlphaISA> _eaCompPtr,
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StaticInstPtr<AlphaISA> _memAccPtr);
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StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
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StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr);
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab);
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};
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@ -1210,10 +1210,12 @@ class MemOperandTraits(OperandTraits):
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def makeWrite(self, op_desc):
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(size, type, is_signed) = operandSizeMap[op_desc.eff_ext]
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eff_type = 'uint%d_t' % size
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return 'fault = xc->write((%s&)%s, EA, %s_flags,' \
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' &%s_write_result);\n' \
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wb = 'fault = xc->write((%s&)%s, EA, %s_flags, &%s_write_result);\n' \
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% (eff_type, op_desc.munged_name, op_desc.base_name,
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op_desc.base_name)
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wb += 'if (traceData) { traceData->setData(%s); }' % \
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op_desc.munged_name
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return wb
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class NPCOperandTraits(OperandTraits):
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def makeConstructor(self, op_desc):
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@ -74,14 +74,6 @@
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using namespace std;
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template<typename T>
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void
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SimpleCPU::trace_data(T data) {
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if (traceData) {
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traceData->setData(data);
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}
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}
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SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
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: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), multiplier(1)
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@ -102,8 +102,7 @@ class SimpleCPU : public BaseCPU
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private:
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Trace::InstRecord *traceData;
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template<typename T>
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void trace_data(T data);
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public:
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//
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enum Status {
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@ -244,6 +243,11 @@ class SimpleCPU : public BaseCPU
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template <class T>
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Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
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// These functions are only used in CPU models that split
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// effective address computation from the actual memory access.
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void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
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Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
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void prefetch(Addr addr, unsigned flags)
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{
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// need to do this...
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@ -1,5 +1,5 @@
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#! /usr/bin/env perl
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# Copyright (c) 2003-2004 The Regents of The University of Michigan
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# Copyright (c) 2003-2005 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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@ -53,7 +53,7 @@ $simargs = '"' . join('" "', @ARGV) . '"';
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# Redirect config output to cout so that gets diffed too (in case
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# that's the source of the problem).
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$simargs += " --Universe:config_output_file=cout";
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$simargs .= " --root:config_output_file=cout";
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$cmd1 = "$sim1 $simargs --stats:text_file=tracediff-$$-1.stats 2>&1 |";
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$cmd2 = "$sim2 $simargs --stats:text_file=tracediff-$$-2.stats 2>&1 |";
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