cpu/ozone/front_end_impl.hh:
cpu/ozone/lw_back_end_impl.hh:
cpu/ozone/lw_lsq_impl.hh:
Support new flags added in.
--HG--
extra : convert_revision : 2e756fd1913cf600650afc39dd715d59b9b89c42
arch/alpha/isa/main.isa:
Use automatic path includes thanks to updates to isa parser.
arch/isa_parser.py:
Pull changes to isa parser from newmem into m5. This fixes a bug where the files include in main.isa were not being included as dependencies properly.
--HG--
extra : convert_revision : 8ef1e2e1a64e7a5762baf7a09abc8665d7c2f688
Need to rewrite bus bridge to get any further.
src/dev/io_device.cc:
Set packet dest on timing responses.
src/mem/bus.cc:
Fix dest addr bounds check assertion.
Add assertion to catch infinite loopbacks.
src/mem/physical.cc:
Add comment.
--HG--
extra : convert_revision : 419b65a3a61e2d099884dbda117b338dffd80896
The "execute" portion of IEW is really just the last cycle of execution, at which point execute() gets called. Execution begins inside the IQ, when it schedules FUs for specific instructions. As a result, the Execute stage should just pull all completing instructions out of the IQ stage and execute them.
Limiting the number of writebacks outstanding must still be done.
cpu/o3/iew_impl.hh:
Rework how instructions are scheduled and executed. There shouldn't be a specific "width" from issue to execute because issue does the scheduling of the functional units (really the beginning of the execution).
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
Rework how instructions are scheduled and executed.
--HG--
extra : convert_revision : bbf1a8a4c0a2f2a938bdd78d74493048fd3b4b55
cpu/checker/cpu.cc:
Cleanup checker, give more useful warning messages.
Also fix bug
cpu/checker/cpu.hh:
Cleanup checker, use forward declaration instead of include.
--HG--
extra : convert_revision : 8f231199a0a75788218320cdbcc7f70441e5d574
arch/alpha/ev5.cc:
Move kernel stats out of CPU and into XC. Also be sure to check if the kernel stats exist prior to using them.
--HG--
extra : convert_revision : 565cd7026410fd7d8586f953d9b328c2e67a9473
IsIprAccess flag may go away in the future (op class can be used to tell this), and the CPU still needs a specific way to identify/deal with syscalls.
arch/alpha/isa/decoder.isa:
Added a few extra flags to help the new CPU identify various classes of instructions without having to force certain behaviors for all CPUs.
cpu/base_dyn_inst.hh:
cpu/static_inst.hh:
Added extra flags.
cpu/o3/iew_impl.hh:
cpu/o3/inst_queue_impl.hh:
Handle store conditionals specially.
cpu/o3/lsq_unit_impl.hh:
Extra flags tells if the instruction is a store conditional.
cpu/o3/rename_impl.hh:
Handle IPR accesses and store conditionals specially.
--HG--
extra : convert_revision : 39debec4fa5341ae8a8ab5650bd12730aeb6c04f
Undo changes to allow multiple build roots in a single
invocation... this would have been too messy to maintain
with the auto-configure stuff, and probably isn't useful anyway.
--HG--
extra : convert_revision : 32a2d9d7fc980911acc3e7b9430df1ba5a0ee68e
It doesn't compile, and if we really want this we should
start over from scratch and see if we can reuse parts from
BaseSimpleCPU (e.g., derive a FastSimpleCPU).
SConstruct:
src/arch/SConscript:
src/cpu/cpu_models.py:
Get rid of FastCPU model.
--HG--
extra : convert_revision : f3f0362f7292bf21e8e0d4d84c475be8a9789a0c
src/arch/sparc/isa/formats/nop.isa:
Fix nop header so we can compile with multiple CPU models.
(Former code re-defined Nop object for each model.)
--HG--
extra : convert_revision : 04e92622edf4dfefd9e149a17f604e17a93707c9
SConstruct:
Clean up libelf handling. Required better handling of
per-build-root stuff in general (though libelf is the
only thing in that category currently).
src/SConscript:
No libelf-specific stuff in here anymore.
src/base/loader/elf_object.cc:
Just need to include gelf.h... it includes libelf.h.
--HG--
extra : convert_revision : 3d6bdcf8233bda0ac8d08ff777de323df8aa45ae
This temporarily will break the O3 and Ozone CPU models. Updates to fix them will be coming soon.
arch/alpha/isa/decoder.isa:
Undo changes to instruction flags that has caused statistics to change in regressions.
--HG--
extra : convert_revision : c0fa9d55a22cae7c4f02d388870565b205d6fba3
cpu/SConscript:
Remove sat_counter.cc and push its functions into the .hh file (all functions were 3 or less lines).
cpu/o3/sat_counter.hh:
Incorporate .cc code into this file.
--HG--
extra : convert_revision : d75b1319292b00b00af1ce377cc0215fd06e6916
Dependecy graph code moved into its own class.
This requires the changes to the functional units, which is in the next check in.
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
IEW and IQ code cleanup and reorganization.
cpu/o3/inst_queue.cc:
Dependency graph code moved into its own class now.
cpu/o3/inst_queue.hh:
IEW/IQ code cleanup and reorganization.
Dependecy graph code moved into its own class.
cpu/o3/inst_queue_impl.hh:
IEW/IQ code cleanup and reorganization.
Dependecy graph code moved into its own class.
Issue loop cleaned up, with completion events for functional units now used more correctly (before they weren't used for multi-cycle ops with pipelined FU's).
--HG--
extra : convert_revision : 35e50192df6f71dc81d46a73fdd65f7ec07c10e4
SConscript:
Split off activity/idling code into its own class to do the processing separately.
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_params.hh:
Activity stuff. This is mostly for debugging and may be removed later on (or changed to enable/disable activity idling).
cpu/o3/cpu.cc:
Move activity idling stuff mostly into its own class, so it no longer clutters this file.
cpu/o3/cpu.hh:
Move activity idling stuff into its own class.
python/m5/objects/AlphaFullCPU.py:
Add parameter for initial activity value.
--HG--
extra : convert_revision : f32f7cc03895dc07ab57ddba78c5402a1a8b0f1a
TimingSimpleCPU. Not there yet.
cpu/simple/atomic.cc:
Only read SC result if store was an SC.
Don't fake SC here; fake it in PhysicalMemory so
all CPU models can share in the joy.
cpu/simple/timing.cc:
Don't forget to checkForInterrupts().
Only fetch subsequent instruction if we're still running
(i.e. not quiesced).
dev/io_device.hh:
Initialize port pointer in SendEvent object.
mem/physical.cc:
Move fake SC "implementation" here from AtomicSimpleCPU.
mem/request.hh:
Initialize flags to all clear, not uninitialized.
Otherwise we can't reliably look at flags w/o explicitly
setting them every time we create a request.
--HG--
extra : convert_revision : ae7601ce6fb54c54e19848aa5391327f9a6e61a6
add sinic back to sconscript file
SConscript:
add sinic back to sconscript file
dev/ide_disk.hh:
add regStats() back to ide_disk
--HG--
extra : convert_revision : a25083993190ceadde977283fbd1fb64e8e7ef86
SConscript:
Comment out sinic for now... needs to be fixed to compile under newmem.
configs/test/SysPaths.py:
Fix paths.
configs/test/fs.py:
SimpleCPU -> AtomicSimpleCPU
Fix vmlinux path
cpu/simple/atomic.cc:
Fix suspendContext() so quiesce works.
Don't forget to checkForInterrupts().
cpu/simple/base.cc:
Minor fix to interrupt check code.
dev/ide_disk.hh:
Don't declare regStats() in header since it's not in
.cc file anymore (will need to add it back in when
stats are added back).
dev/io_device.cc:
Set packet dest to Packet::Broadcast.
dev/pciconfigall.cc:
Set PCI config packet result to Success.
python/m5/objects/Root.py:
Add debug object to Root so things like break_cycles
can be set from command line.
--HG--
extra : convert_revision : aa1c652fe589784e753e13ad9acb0cd5f3b6eafb
cpu/checker/cpu.cc:
Fixups for fetch fault being sent with the instruction.
cpu/o3/fetch_impl.hh:
cpu/ozone/front_end_impl.hh:
Send any faults generated at fetch along with a fake nop instruction to the back end. This avoids having to use direct communication to check if the entire front end has drained; it is naturally handled through the nop's fault being handled when it reaches the head of commit.
cpu/ozone/front_end.hh:
Add extra status TrapPending.
cpu/ozone/lw_back_end_impl.hh:
Fetch fault handled through a dummy nop carrying the fetch fault.
Avoid putting Nops on the exeList.
--HG--
extra : convert_revision : 8d9899748b34c204763a49c48a9b5113864f5789
TimingSimpleCPU, which use atomic and timing memory accesses
respectively. Common code is factored into the BaseSimpleCPU class.
AtomicSimpleCPU includes an option (simulate_stalls) to add delays
based on the estimated latency reported by the atomic accesses.
Plain old "SimpleCPU" is gone; I have not updated all the config
files (just test/test.py).
Also fixes to get timing accesses working in new memory model and
to get split-phase memory instruction definitions working with
new memory model as well.
arch/alpha/isa/main.isa:
Need to include packet_impl.h for functions that use Packet objects.
arch/alpha/isa/mem.isa:
Change completeAcc() methods to take Packet object pointers.
Also split out StoreCond template for completeAcc(), since
that's the only one that needs write_result and we get an
unused variable warning if we always have it in there.
build/SConstruct:
Update list of recognized CPU model names.
configs/test/test.py:
Change SimpleCPU to AtomicSimpleCPU.
cpu/SConscript:
Define sources for new CPU models.
Add split memory access methods to CPU model signatures.
cpu/cpu_models.py:
cpu/static_inst.hh:
Define new CPU models.
cpu/simple/base.cc:
cpu/simple/base.hh:
Factor out pieces specific to Atomic or Timing models.
mem/bus.cc:
Bus needs to be able to route timing packets based on explicit dest
so responses can get back to requester. Set dest to Packet::Broadcast
to indicate that dest should be derived from address.
Also set packet src field based on port from which packet is sent.
mem/bus.hh:
Set packet src field based on port from which packet is sent.
mem/packet.hh:
Define Broadcast destination address to indicate that
packet should be routed based on address.
mem/physical.cc:
Set packet dest on response so packet is routed
back to requester properly.
mem/port.cc:
Flag blob packets as Broadcast.
python/m5/objects/PhysicalMemory.py:
Change default latency to be 1 cycle.
--HG--
rename : cpu/simple/cpu.cc => cpu/simple/base.cc
rename : cpu/simple/cpu.hh => cpu/simple/base.hh
extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132
cpu/ozone/cpu.hh:
Updates for sampler.
cpu/ozone/cpu_impl.hh:
Updates for sampler, checker.
cpu/ozone/inorder_back_end.hh:
Sampler updates. Also support old memory system.
--HG--
extra : convert_revision : 33ebe38e4c08d49c6af84032b819533b784b4fe8
cpu/o3/alpha_cpu.hh:
Update for sampler to work properly. Also code cleanup.
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_dyn_inst.hh:
Updates to support the checker.
cpu/o3/alpha_cpu_impl.hh:
Updates to support the checker. Also general code cleanup.
cpu/o3/alpha_dyn_inst_impl.hh:
Code cleanup.
cpu/o3/alpha_params.hh:
Updates to support the checker. Also supports trap latencies set through the parameters.
cpu/o3/commit.hh:
Supports sampler, checker. Code cleanup.
cpu/o3/commit_impl.hh:
Updates to support the sampler and checker, as well as general code cleanup.
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
Support sampler and checker.
cpu/o3/decode_impl.hh:
Supports sampler.
cpu/o3/fetch.hh:
Supports sampler. Also update to hold the youngest valid SN fetch has seen to ensure that the entire pipeline has been drained.
cpu/o3/fetch_impl.hh:
Sampler updates. Also be sure to not fetches to uncached space (bad path).
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
Sampler updates.
cpu/o3/lsq_unit_impl.hh:
Supports checker.
cpu/o3/regfile.hh:
No need for accessing xcProxies directly.
cpu/o3/rename.hh:
cpu/o3/rename_impl.hh:
Sampler support.
--HG--
extra : convert_revision : 03881885dd50ebbca13ef31f31492fd4ef59121c
base/traceflags.py:
build/SConstruct:
cpu/SConscript:
cpu/cpu_models.py:
Add in Checker.
cpu/base.cc:
Add in checker support. Also XC status starts off as suspended.
cpu/base.hh:
Add in checker.
--HG--
extra : convert_revision : 091b5cc83e837858adb681ef0137a0beb30bd1b2
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
Sampling fixes. The CPU models may switch during a quiesce period, so it needs to be sure to wake up the right XC.
cpu/exec_context.hh:
Return the EndQuiesceEvent specifically.
sim/pseudo_inst.cc:
Return the EndQuiesceEvent specifically for sampling.
--HG--
extra : convert_revision : f9aa1fc8d4db8058f05319cb6a3d4605ce93b4c8
arch/alpha/isa/decoder.isa:
Mark store conditionals as serializing. This is slightly higher over head than they truly have in the 264, but it's close. Normally they block any other instructions from entering the IQ until the IQ is empty. This is higher overhead because it waits until the ROB is empty.
Also mark RPCC as unverifiable. The checker will just grab the value from the instruction and assume it's correct.
cpu/static_inst.hh:
Add unverifiable flag, specifically for the CheckerCPU.
--HG--
extra : convert_revision : cbc34d1f2f5b07105d31d4bd8f19edae2cf8158e
Get rid of more unneeded includes.
base/hostinfo.cc:
base/inet.cc:
base/remote_gdb.cc:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/disk_image.cc:
dev/ns_gige.cc:
dev/sinic.cc:
mem/physical.cc:
sim/param.cc:
sim/process.cc:
sim/pseudo_inst.cc:
test/cprintftest.cc:
Get rid of more unneeded includes.
--HG--
extra : convert_revision : f531ae40db3787f2c55df7d251f251ecae4ab731
into zeep.pool:/z/saidi/work/m5.newmem
base/loader/elf_object.cc:
removed SPARC32PLUS since it doesn't work.
--HG--
extra : convert_revision : 620a1c75cdeefbeeb97383d92335cf319d9c9444
