Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.
SConstruct:
Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add option to try raw when nothing works
src/cpu/exetrace.cc:
cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
change the instruction to be 32 bits because it is
src/mem/physical.cc:
fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
add the ability to add Addr() together
--HG--
extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
configs/common/Simulation.py:
Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU.
However the O3CPU must always use caches, so a check for that must still exist.
Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU.
configs/example/fs.py:
configs/example/se.py:
Atomic CPU now handles caches.
--HG--
extra : convert_revision : 534ded558ef96cafd76b4b5c5317bd8f4d05076e
configs/common/Simulation.py:
simplify maxtick code a little bit - instead of checking for -1, just set it at MaxTick.
src/python/m5/__init__.py:
make a new m5 param called MaxTick.
src/sim/host.hh:
fix the M5 def. of MaxTick
src/sim/main.cc:
Simplify the MaxTick/num_cycles parsing within main.cc
--HG--
extra : convert_revision : f800addfbc1323591c2e05b892276b439b671668
configs/common/Simulation.py:
enable going from checkpoint into arbitrary CPU with or without caches.
--HG--
extra : convert_revision : 02e7ff8982fdb3a08bc609f89bd58df5b3a581b2
configs/common/Simulation.py:
Remove mem parameter.
configs/example/se.py:
Remove debug output that got included in my other push.
--HG--
extra : convert_revision : 643c34147f6c6cbb98b8e6d6e8206b9859593ab0
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
configs/example/fs.py:
configs/example/se.py:
src/mem/tport.hh:
Hand merge.
--HG--
extra : convert_revision : b9df95534d43b3b311f24ae24717371d03d615bf
configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
No need for mem parameter any more.
src/cpu/checker/cpu.cc:
Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
Remove memory parameter.
--HG--
extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
Accidentally committed this last time
configs/common/FSConfig.py:
Accidentally committed this last time
--HG--
extra : convert_revision : 32d49c17c661b57a9aa9c3b057258f6e037ba745
configs/common/Options.py:
make the warmup period in a standard switch part of the option.
configs/common/Simulation.py:
add some comments and also make the warmup period an option.
--HG--
extra : convert_revision : 0fa587291b97ff87c3b3a617e7359ac6d9bed7a5
configs/example/fs.py:
factor out common code.
configs/example/se.py:
factor out common code
--HG--
extra : convert_revision : 72a1f653c84eae1b7d281e0a5e60ee116ad6b27d
1) rearrange the options to be in a nice logical order
2) add an option for what i call "standard switch", which is from simple->timing->detailed
3) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
4) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first
--HG--
extra : convert_revision : 8d905e1b297ae664d60f8c8ba48b2aac25437fc6
1) rearrange the options to be in a nice logical order
2) add an option for what i call "standard switch", which is from simple->timing->detailed
3) change the client/server naming system to testsys/drivesys
4) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
5) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first
doesn't fully work because of a caching issue, but the python side of things i think should work - the counterpart of se.py does work.
i think i should factor out a lot of the common code in both, but i'll do that after this checkin, just to get this in the tree.
configs/example/fs.py:
1) rearrange the options to be in a nice logical order
2) add an option for what i call "standard switch", which is from simple->timing->detailed
3) change the client/server naming system to testsys/drivesys
4) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries.
5) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first
--HG--
extra : convert_revision : 078e22800ff83f6e950bf5cc6fb16a98320e7c51
configs/example/fs.py:
Add MOESI protocol to caches (uni coherence not quite working w/FS yet).
--HG--
extra : convert_revision : 7bef7d9c5b24bf7241cc810df692408837b06b86
configs/example/fs.py:
Add flag for MP server systems.
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/IntrControl.py:
Change CPU from 'any' to 'cpu[0]' to work better with MP sytems.
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-timing-dual.py:
Don't need to set console & intrcontrol cpu
params anymore (default is fixed now).
--HG--
extra : convert_revision : 9417b12b1b395ff7d6a9f2894e4123923c754daf
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
Hand merge.
--HG--
extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
so you can restore by a command line like this:
m5.opt fs.py --checkpoint_dir="/my/ckpt/dir" -c 3
configs/example/fs.py:
add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N.
--HG--
extra : convert_revision : bf9c8d3265a3875cdfb6a878005baa7ae29af90d
configs/common/FSConfig.py:
configs/common/SysPaths.py:
configs/example/fs.py:
configs/example/se.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
Clean up configs by removing FullO3Config and instead using default values.
src/python/m5/objects/FUPool.py:
Add in default FUPool.
src/python/m5/objects/O3CPU.py:
Use defaults better. Also set checker parameters, and fix up a config bug.
--HG--
extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b
Significant revamp of Port code.
Some cleanup of SimObject code too, particularly to
make the SimObject and MetaSimObject implementations of
__setattr__ more consistent.
Unproxy code split out of print_ini().
src/python/m5/multidict.py:
Make get() return None by default, to match semantics
of built-in dictionary objects.
--HG--
extra : convert_revision : db73b6cdd004a82a08b2402afd1e16544cb902a4
