Commit graph

99 commits

Author SHA1 Message Date
Kevin Lim
21df09cf7a Fixes for ozone CPU to successfully boot and run linux.
cpu/base_dyn_inst.hh:
    Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
    Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
    Fixes for store conditionals.  Use an additional lock addr list to make sure that the access is valid.  I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
    Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
    Also support the new Checker.
cpu/ozone/cpu_builder.cc:
    Add parameter for maxOutstandingMemOps so it can be set through the config.
    Also add in the checker.  Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
    Add support for the checker.  For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type.  It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.

    Support switching out/taking over from other CPUs.

    Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
    Add ability for instructions to wait on memory instructions in addition to source register instructions.  This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
    Support waiting on memory operations.
    Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
    Support switching out.
    Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
    Support switching out.  Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
    Add checker in.
    Support switching out.
    Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
    Lots of changes to get things to work right.
    Faults, traps, interrupts all wait until all stores have written back (important).
    Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
    Support switching out.
    Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
    Support switching out.
    Also use store writeback events in all cases, not just dcache misses.
    Support the checker CPU.  Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
    Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
    Add max outstanding mem ops, checker.

--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
2006-05-11 19:18:36 -04:00
Kevin Lim
f0baf0ec99 Update the python file for the CPU.
--HG--
extra : convert_revision : be899403d893f5ab6c11ae5a4334c0e36bd6ff61
2006-04-22 18:47:07 -04:00
Kevin Lim
759ff4b910 Updates for OzoneCPU.
build/SConstruct:
    Include Ozone CPU models.
cpu/cpu_models.py:
    Include OzoneCPU models.

--HG--
extra : convert_revision : 51a016c216cacd2cc613eed79653026c2edda4b3
2006-04-22 18:45:01 -04:00
Kevin Lim
a8b03e4d01 Updates for O3 model.
arch/alpha/isa/decoder.isa:
    Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
    Allow IPR instructions to have flags.
base/traceflags.py:
    Include new trace flags from the two new CPU models.
cpu/SConscript:
    Create the templates for the split mem accessor methods.  Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
    Update to the BaseDynInst for the new models.

--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
2006-04-22 18:26:48 -04:00
Ali Saidi
d01a593433 move alpha specific code into arch/alpha
System -> AlphaSystem

SConscript:
    Move some more files around
arch/alpha/freebsd/system.cc:
arch/alpha/freebsd/system.hh:
    System -> AlphaSystem
arch/alpha/linux/aligned.hh:
arch/alpha/linux/hwrpb.hh:
arch/alpha/linux/system.cc:
arch/alpha/linux/thread_info.hh:
arch/alpha/linux/threadinfo.hh:
    move alpha specific code into arch/alpha
python/m5/objects/System.py:
    Split off arch specific parts of system into AlphaSystem

--HG--
rename : kern/freebsd/freebsd_system.cc => arch/alpha/freebsd/system.cc
rename : kern/freebsd/freebsd_system.hh => arch/alpha/freebsd/system.hh
rename : kern/linux/aligned.hh => arch/alpha/linux/aligned.hh
rename : kern/linux/hwrpb.hh => arch/alpha/linux/hwrpb.hh
rename : kern/linux/linux_system.cc => arch/alpha/linux/system.cc
rename : kern/linux/linux_system.hh => arch/alpha/linux/system.hh
rename : kern/linux/thread_info.hh => arch/alpha/linux/thread_info.hh
rename : kern/linux/linux_threadinfo.hh => arch/alpha/linux/threadinfo.hh
rename : kern/tru64/tru64_system.cc => arch/alpha/tru64/system.cc
rename : kern/tru64/tru64_system.hh => arch/alpha/tru64/system.hh
extra : convert_revision : 1c496efb823326a4b629574bd9b5f30e99a0aa40
2006-03-04 20:45:01 -05:00
Nathan Binkert
7546fabe68 Ethernet devices have an RSS option to tell the driver to
use Receive side scaling

dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/sinic.cc:
dev/sinic.hh:
dev/sinicreg.hh:
    add support for setting the RSS flag to notify the driver
    to use RSS

--HG--
extra : convert_revision : 5f0c11668ae976634b3bf0caad669a9464a4c041
2006-03-03 14:17:48 -05:00
Nathan Binkert
3a0102536b Get rid of the code that delays PIO write accesses
until the cache access occurs.  The fundamental problem
is that a subsequent read that occurs functionally will
get a functionally incorrect result that can break
driver code.

dev/ns_gige.cc:
dev/ns_gige.hh:
dev/sinic.cc:
dev/sinic.hh:
    get rid of pio_delay write and the associated code to move
    the write to the cache access function
dev/sinicreg.hh:
    no more write delays
python/m5/objects/Ethernet.py:
    get rid of pio_delay write

--HG--
extra : convert_revision : 1dcb51b8f4514e717bc334a782dfdf06d29ae69d
2006-02-20 23:41:50 -05:00
Nathan Binkert
47ff0af17e Virtualize sinic
separate the rx thread and tx thread and get rid of the dedicated flag.

dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
python/m5/objects/Ethernet.py:
    dedicated flag goes away, we have new individual flags for
    rx thread and tx thread
dev/sinic.cc:
    Virtualize sinic
    - The io registers are replicated many times in memory, allowing the NIC to
    differentiate among several virtual interfaces.
    - On the TX side, this allows multiple CPUs to initiate transmits at the same
    time without locking in the software.  If a partial packet is transmitted,
    then the state machine blocks waiting for that virtual interface to complete
    its packet.  Then the state machine will move on to the next virtual
    interface.  The commands are kept in fifo order.
    - On the RX side, multiple partial transmits can be simultaneously done.
    Though a packet does not deallocate its fifo space until all preceeding
    packets in the fifo are deallocated.  To enable multiple receives, it
    is necessary for each virtual nic to keep its own information about its
    progress through the state machine.
dev/sinic.hh:
    Virtualize sinic
    Receive state must be virtualized since we allow the receipt of packets in
    parallel.
dev/sinicreg.hh:
    Virtualize sinic
    separate rx thread and tx thread
    create a soft interrupt and add a command to trigger it.
    pad out the reserved bits in the RxDone and TxDone regs

--HG--
extra : convert_revision : c10bb23a46a89ffd1e08866c1f1621cb98069205
2005-11-25 13:33:36 -05:00
Nathan Binkert
f806a25c9e add support for delaying pio writes until the cache access occurs
dev/ns_gige.cc:
    add support for delaying pio writes until the cache access occurs
    the only write we delay are for CR_TXE and CR_RXE
dev/sinic.cc:
dev/sinic.hh:
    the txPioRequest and rxPioRequest things were more or less bogus
    add support for delaying pio writes until the cache access occurs
dev/sinicreg.hh:
    Add delay_read and delay_write to the register information struct
    for now, we won't delay any reads, and we'll delay the writes that
    initiate DMAs
python/m5/objects/Ethernet.py:
    add a parameter to delay pio writes until the timing access
    actually occurs.

--HG--
extra : convert_revision : 79b18ea2812c2935d7d5ea6eff1f55265114d05d
2005-11-21 23:43:15 -05:00
Nathan Binkert
d3a4781ac5 Actually, you should'nt do math on Clock in the config files.
python/m5/config.py:
    Clock should not be a NumericParamValue since math on it can be
    ambiguous.  (As the comment clearly says.)

--HG--
extra : convert_revision : 74f8ec846c6a980d92e0bf4bf1c7fac73a75b923
2005-11-21 00:22:29 -05:00
Nathan Binkert
c4678ece84 BARs now of type MemorySize32
python/m5/config.py:
    Add MemorySize32 (a 32-bit value specified in bytes)

--HG--
extra : convert_revision : bfeee501f7ff1aa2567a3682da129a5770cb7bd2
2005-11-21 00:02:39 -05:00
Nathan Binkert
d733d168ca Make it so one can do math with a Clock type in the config files
python/m5/config.py:
    Make Clock a NumericParamValue so you can do math with it

--HG--
extra : convert_revision : 7fa548d1a23c604a31d3ecae3853949b064a1830
2005-11-20 23:57:26 -05:00
Nathan Binkert
3b8b838417 Allow long as a multiplier in the python config
python/m5/config.py:
    Allow long as a multiplier

--HG--
extra : convert_revision : bdc45e9afc27bb7b0f2cd6aacf92758601b95ff8
2005-11-20 23:45:45 -05:00
Nathan Binkert
12d903a650 io_bus is split out into pio_bus and dma_bus so that any device
can specify either independently.

python/m5/objects/Device.py:
    io_bus is split out into pio_bus and dma_bus so that any device
    can specify either independently.
    dma_bus defaults to point to whatever pio_bus uses.

--HG--
extra : convert_revision : d35d5374d0bf592f6b5df465c05203577b8b8763
2005-11-20 16:57:53 -05:00
Ali Saidi
cb929af345 allow conversion floats -> long so that 100e9 and such work as Ticks
--HG--
extra : convert_revision : 23511baca6153bb3aa9c57be8818ad1b65f02a71
2005-11-02 15:37:47 -05:00
Ali Saidi
3b66cb49ec Merge zizzer:/bk/m5
into  zeep.eecs.umich.edu:/z/saidi/work/m5

--HG--
extra : convert_revision : 3cc23080d19cc464a8ba7c1c93b6e5d45af7d463
2005-11-02 14:56:18 -05:00
Ali Saidi
15ccd16fd8 Add Mem/Ethernet latency variability parameter
python/m5/objects/Ethernet.py:
    Add Latency Variability Parameter

--HG--
extra : convert_revision : db5431cccffea8c7247d0f72e4770d4d58bd25aa
2005-11-02 14:44:42 -05:00
Nathan Binkert
dd46db1cb9 __init__ should not return anything
--HG--
extra : convert_revision : fb46eee741f4899d76bcf927523fa151d002decf
2005-11-02 12:14:26 -05:00
Steve Reinhardt
d238b6be9d Make vector params interact with proxies properly.
--HG--
extra : convert_revision : a4067f07d71d2adc1ccbf4512a43ceee7b5cc3de
2005-11-02 10:20:39 -05:00
Steve Reinhardt
fb4f83809f Allow math on CheckedInt-derived ParamValue classes w/o
losing type information.

python/m5/config.py:
    Allow math on CheckedInt-derived ParamValue classes w/o
    losing type information.
    - Make CheckedInt derive from NumericParamValue, and *not*
    multiply inherit from long
    - Move CheckedInt bounds check to _check() hook so we can
    call it when value is updated (not just in constructor)
python/m5/convert.py:
    - make toInteger() return a long, making toLong() unnecessary
    - toMemorySize should return long rather than float

--HG--
extra : convert_revision : c1cf5e15b9ff35d9b573dd545e076fe68afef989
2005-11-01 14:11:54 -05:00
Nathan Binkert
b7b8ffa7b7 Major changes to sinic device model. Rearrage read/write, better
interrupts.

dev/sinic.cc:
    - The prepareRead function sets all the variables in the register
    file that depend on various state bits that change on the fly.
    Includes RxDone, RxWait, TxDone, and TxWait
    - Use the new register information accessor functions to grab
    validity and size information for the read and write functions
    - read all registers directly from the register space by offset
    and size, not by actual name (less code)
    - The side effect of reading the interrupt status (clearing it) now
    happens outside the actual chunk of code where the value is loaded.
    - Add an iprRead function for when we may want speculative access
    to device registers through an ipr or special instruction.
    - When RxData or TxData are written, their busy flag is set to
    indicate that they have an outstanding transaction.
    - The RxHigh and TxLow interrupts are special, they only interrupt
    if the rxEmpty or txFull limits were hit
    - Move reset to the command register
    - Update more registers on reset, clear rxEmpty and txFull
    - Data dumps only happen if EthernetData trace flag set
    - When a DMA completes, kick the other engine if it was waiting
    - implement all of the new interrupts
    - serialize the new stuff
dev/sinic.hh:
    - Put all registers with their proper size and alignment into
    the regs struct so that we can copy multiple at a time.
    - Provide accessor functions for accessing the registers with
    different sizes.
    - Flags to track when the rx fifo hit empty and the tx fifo became
    full.  These flags are used to determine what to do when below
    the watermarks, and are reset when crossing the watermark.
    - the txDmaEvent should actually trigger the txDmaDone function
    - Add an iprRead function for when we may want speculative access
    to device registers through an ipr or special instruction.
    - The prepareRead function sets all the variables in the register
    file that depend on various state bits that change on the fly.
    - add rx_max_intr and dedicated (for dedicated thread) config params
dev/sinicreg.hh:
    Add some new registers: Command, RxMaxIntr, RxFifoSize, TxFifoSize,
    rename XxThreshold to XxFifoMark
    Move Reset to the Command register
    Add Thread to the Config register
    New interrupts, better names
    More info in RxDone and TxDone
    Easier access to information on each register (size, read, write, name)
python/m5/objects/Ethernet.py:
    Both sinic and nsgige have the dedicated thread
    Add a parameter to configure the maximum number for receive
    packets per interrupt

--HG--
extra : convert_revision : 407c5a993b6fb17326b4c623ee5d4b25fd69ac80
2005-10-21 20:28:21 -04:00
Nathan Binkert
2badc0113c Shuffle around device names to make things easier to read.
Create EtherDevBase which both Sinic and NSGigE derive from
bump fifos
drop rx max copy size to 1514 bytes to be friendlier with linux
default interrupt delay is 10us

dev/ns_gige.cc:
    Shuffle around parameters to make it easier to find stuff
dev/sinic.cc:
    Shuffle around parameters to make it easier to find stuff
    rename cycleTime -> clock
dev/sinic.hh:
    rename cycleTime -> clock

--HG--
extra : convert_revision : a673bee875e50d083098991aea20972fa8d5b5c7
2005-10-18 22:05:05 -04:00
Nathan Binkert
4f43bc65ea use the dedicated flag, no more exposing the m5reg directly
dev/ns_gige.cc:
    stop exposing the m5reg to the configuration stuff and build it
    based on exposed flags.  Expose dedicated now.
dev/ns_gige.hh:
    goodbye m5reg hello dedicated
dev/ns_gige_reg.h:
    Flags for the M5REG

--HG--
extra : convert_revision : 11134fe67cdf5291caacf9b3041739c437b983e3
2005-10-18 21:01:05 -04:00
Steve Reinhardt
af2a600f99 Add execution trace object to Root.
python/m5/objects/Root.py:
    Add execution trace object.

--HG--
extra : convert_revision : 1d1ba18779fd4d0b5af921c5f34b7a2bfb4b75d9
2005-10-06 13:50:13 -04:00
Steve Reinhardt
93e60de656 Add executable parameter to LiveProcess. This allows the argv[0] value to
stay fixed even if the path to the binary changes, so the simulation results
are independent of that path.

--HG--
extra : convert_revision : d1109cd284466c14eddc97289908a51e771fc5db
2005-10-01 16:02:47 -04:00
Nathan Binkert
f88d7c7456 Fix the EtherDump parameters
dev/etherdump.cc:
    no default parameters anymore they should be in python
python/m5/objects/Ethernet.py:
    move the maxlen parameter for EtherDump into python

--HG--
extra : convert_revision : a796353a68907dfeb22059cd3ad536e6e8f60998
2005-09-17 10:47:16 -04:00
Steve Reinhardt
845bdb0d8e Regression tests now run under scons!
For example, 'scons ALPHA_SE/test/opt/quick' will build
ALPHA_SE/m5.opt if necessary and run all the self-identified
"quick" tests on it.  Other possibilities:
- Run just test1: scons ALPHA_SE/test/opt/test1
- Run all tests:  scons ALPHA_SE/test/opt
- Run all tests on debug build: scons ALPHA_SE/test/debug
- Update test1 reference outputs in m5-test:
scons update_ref=y ALPHA_SE/test/opt/test1
The proper tests will be selected based on the setting
of FULL_SYSTEM, ALPHA_TLASER, etc.

README:
    Update directions to use scons-based test invocation.
SConscript:
    Return list of generated build environments to SConstruct
    so it can associate tests with each of them.
    Set 'M5Binary' attribute on each env to record name of
    generated binary to be tested.
build/SConstruct:
    - Support invoking m5-test tests via scons.
    - Add new non-sticky option category, for 'update_ref'.
    - Move existing "sticky" option definitions out of
    build_dir loop.  Someday we can generate help text
    from these.
    - Make 'CC' and 'CXX' sticky options; use environment vars as
    defaults if available.
    - Make config builder more scons-y.
python/m5/__init__.py:
    Make AddToPath() correctly handle relative path arguments.
    Assumes that sys.path[0] has the directory where the current
    Python file lives; new m5execfile() function sets this up
    properly for exec'd files.

--HG--
extra : convert_revision : 48896688592e210d8e63f96c34e57474853d0e66
2005-09-05 16:31:27 -04:00
Steve Reinhardt
23a9102d01 Convert type of max_time and progress_interval parameters
from Latency to Tick, and rename max_time to max_tick.

python/m5/objects/Root.py:
sim/root.cc:
    Convert type of max_time and progress_interval
    from Latency to Tick, and rename max_time to max_tick.

--HG--
extra : convert_revision : 2f2aacf6321c3003a0ce834acd8fb726abf27ce3
2005-09-01 11:32:58 -04:00
Steve Reinhardt
c4793184bd Build options are set via a build_options file in the
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line.  Build option flags are now always
defined to 0 or 1, so checks must use '#if' rather than
'#ifdef'.

SConscript:
    MySQL detection moved to SConstruct.
    Add config/*.hh files (via ConfigFile builder).
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/isa_traits.hh:
base/fast_alloc.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/regfile.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob_impl.hh:
cpu/ozone/cpu.hh:
cpu/pc_event.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
sim/process.cc:
sim/process.hh:
    Convert compile flags from def/undef to 0/1.
    Set via #include config/*.hh instead of command line.
arch/alpha/isa_desc:
    Convert compile flags from def/undef to 0/1.
    Set via #include config/*.hh instead of command line.
    Revamp fenv.h support... most of the ugliness is hidden
    in base/fenv.hh now.
base/mysql.hh:
    Fix typo in #ifndef guard.
build/SConstruct:
    Build options are set via a build_options file in the
    build directory instead of being inferred from the name
    of the build directory.
    Options are passed to C++ via config/*.hh files instead of
    via the command line.
python/SConscript:
    Generate m5_build_env directly from scons options
    instead of indirectly via CPPDEFINES.
python/m5/convert.py:
    Allow '0' and '1' for booleans.
    Rewrite toBool to use dict.
base/fenv.hh:
    Revamp <fenv.h> support to make it a compile option
    (so we can test w/o it even if it's present) and to
    make isa_desc cleaner.

--HG--
extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
2005-08-30 13:18:54 -04:00
Benjamin Nash
0d82e0f8b6 Merge m5.eecs.umich.edu:/bk/m5
into  zed.eecs.umich.edu:/z/benash/bk/m5

--HG--
extra : convert_revision : 36bb126381caf84d85a566579225b02c15f8f356
2005-08-16 15:27:39 -04:00
Miguel Serrano
b64eae5e52 Changes for getting FreeBSD to run.
SConscript:
    Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
    Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks().
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
    Replaced htoa()s with gtoh() and htog().
cpu/o3/fetch_impl.hh:
cpu/simple/cpu.cc:
    Replaced htoa() with gtoh().
dev/disk_image.cc:
    Replaced htoa()s with letoh()s.
dev/ide_ctrl.cc:
    Got rid of magic numbers.
    Added IdeChannel and IdeRegType type names where necessary.
dev/ide_ctrl.hh:
    Got rid of unnecessary macros.
    Changed RegType_t to IdeRegType.
    Changed bmi_regs to allow accessing registers by name instead of just by array index.
    Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel.
dev/ide_disk.cc:
    Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array.
dev/ide_disk.hh:
    Updated command register struct.
dev/ns_gige.cc:
dev/ns_gige.hh:
    Made ReadConfig and WriteConfig begin with a lower-case letter.
    writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pciconfigall.cc:
    writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pcidev.cc:
    Cleaned up readConfig() and writeConfig() functions.
dev/pcidev.hh:
    Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data.
dev/pcireg.h:
    Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used.
dev/rtcreg.h:
    Added macros for bit fields in RTC status registers A & B.
dev/sinic.cc:
    Function name change: WriteConfig --> writeConfig.
    writeConfig() now takes a pointer to data instead of a copy of data.
    The accessing of elements of PCIConfig structure is updated.
dev/sinic.hh:
    Function name change: WriteConfig --> writeConfig.
    writeConfig() now takes a pointer to data instead of a copy of data.
dev/tsunami_io.cc:
    Added implementation of new RTC and PIT classes.
dev/tsunami_io.hh:
    Added classes for RTC and PIT modules.
dev/tsunamireg.h:
    Added macros for DMA ports used by Tsunami-Tru64.
dev/uart8250.cc:
    Got rid of a magic number.
    Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register.
dev/uart8250.hh:
    Added comments and macros dealing with the UART Interrupt ID register.
kern/linux/linux_system.cc:
    Replaced htoa() with htog().
python/m5/objects/Pci.py:
    PciFake is a python class for Pci Devices that do nothing.
python/m5/objects/Tsunami.py:
    TsunamiFake was renamed as IsaFake.
sim/system.cc:
    Replaced htoa()s with htog()s.
dev/isa_fake.cc:
    New BitKeeper file ``dev/isa_fake.cc''
    TsunamiFake was renamed as IsaFake.
dev/isa_fake.hh:
    New BitKeeper file ``dev/isa_fake.hh''
    TsunmaiFake was renamed as IsaFake.
dev/pitreg.h:
    New BitKeeper file ``dev/pitreg.h''
    Useful macros for working with PIT (Periodic Interval Timer) registers.

--HG--
extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780
2005-08-15 16:59:58 -04:00
Nathan Binkert
38da461fd7 Fix NextEthernetAddr
python/m5/config.py:
    NextEthernetAddr shouldnt' be a Singleton since we want __init__ to be
    called more than once.
    Make the EthernetAddr class a "proxy" so that unproxy will
    be called and NextEthernetAddr will generally work correctly.

--HG--
extra : convert_revision : c89bf268e805e202ae71030fcea4833867c7e477
2005-08-15 16:12:19 -04:00
Steve Reinhardt
1e2c16c912 Fix for passing functional memory param to timing mem.
python/m5/config.py:
    Fix error message.

--HG--
extra : convert_revision : 4e57f7bdd4ea7dfdd3e88c60080f993997b0bda2
2005-07-18 19:58:43 -04:00
Nathan Binkert
8a0bc84022 Allow CPUs to specify their own CPU ids.
Make the AlphaConsole calculate the number of CPUs instead
of passing that in as a parameter.

cpu/base.cc:
    pass the desired cpu_id into registerExecContext, offsetting it
    by the thread number.  a cpu_id of -1 means that it should be
    generated for you.
cpu/base.hh:
    Take the cpu_id as a parameter
cpu/o3/alpha_cpu_builder.cc:
cpu/simple/cpu.cc:
    Accept the cpu_id as a parameter
    while we're here, let's remove the multiplier since it is
    not used.
dev/alpha_console.cc:
    don't take the number of CPUs as a parameter.  Calculate it from
    the system based on the number of CPUs that have been registered.
    move init() code to startup() to ensure that all CPUs are registerd.
dev/alpha_console.hh:
python/m5/objects/AlphaConsole.py:
    don't take the number of CPUs as a parameter.
    move init() code to startup() to ensure that all CPUs are registerd.
python/m5/objects/BaseCPU.py:
    take the cpu_id as a parameter.  Default it to -1 which means
    that it will be generated.
sim/system.cc:
    allow the registerExecContext functioin to take a desired
    cpu_id as a parameter.  Check to ensure that the id isn't
    already used.  Accept -1 as a request to have an id assigned.
sim/system.hh:
    keep track of the number of registered exec contexts.
    provide a function for accessing the number of exec contexts
    that checks to ensure that they are all registered correctly.

--HG--
extra : convert_revision : 8e12f96ff8a49fa16cdbbdb4c05c651376c35788
2005-06-29 01:20:41 -04:00
Nathan Binkert
c4029ecb30 Implement a state machine clock that acutally limits how fast
the nsgige state machine can run. The frequency is of the actual
state transitions, and not the rate of what underlying
instructions might run at.

dev/ns_gige.cc:
    Implement a state machine clock that acutally limits how fast
    the state machine can run.  After each state transition, a
    variable is kept to hold the next state transition until the
    next clock.  The frequency is of the actual state transitions,
    and not the rate of what underlying instructions might run at.
dev/ns_gige.hh:
    Add back the rxKickEvent and txKickEvent events.
python/m5/objects/Ethernet.py:
    Default the state machine clock to '0ns' so the default
    behaviour doesn't change when we actually implement the
    state machine clock.

--HG--
extra : convert_revision : 2db1943dee4e91ea75aaee6a91e88f27f01a09dd
2005-06-27 17:02:40 -04:00
Ali Saidi
cad549d7aa Added Float class
Fixed printing so the tokenizer in m5 doesn't get confused
Expanded NullSimObject so it could be used as an element in a VectorParam

--HG--
extra : convert_revision : 661b1916967d663ab7aee891f15f7ca190deeba6
2005-06-23 01:07:04 -07:00
Nathan Binkert
91f5736fd3 Move max_time and progress_interval parameters to the Root
object and get rid of the ParamContext that each used to have.

python/m5/objects/Root.py:
    Add max_time and progress_interval to the Root object
sim/root.cc:
    Add max_time and progress_interval to the Root object.  These
    parameters used to be in their own contexts in sim_events.cc
sim/sim_events.cc:
    Get rid of the ParamContext for max cycles and the progress
    event.  Move the functionality to the Root object
sim/sim_events.hh:
    Move ProgressEvent declaration to the header so that it can
    be used in other files.

--HG--
extra : convert_revision : ff664b806855e8eb9201b8a25392aa53204464f0
2005-06-22 09:59:13 -04:00
Nathan Binkert
ebb35e57ce BaseSystem was renamed to System
--HG--
extra : convert_revision : 74e03fe9447d9d2be59e675b034dc6df0afcde51
2005-06-09 15:09:35 -04:00
Nathan Binkert
8522474318 Merge zizzer.eecs.umich.edu:/bk/m5
into crampon.my.domain:/z/binkertn/research/m5/head

--HG--
extra : convert_revision : eb0e28e22549f875cef25043491a30c2755676ed
2005-06-05 02:26:18 -04:00
Steve Reinhardt
d4559c32e4 Add licenses in python dir.
python/m5/__init__.py:
python/m5/convert.py:
python/m5/multidict.py:
python/m5/smartdict.py:
    Add license.

--HG--
extra : convert_revision : 825dcad94e13b18aadc7188053ad1999a0219eae
2005-06-05 01:57:57 -04:00
Nathan Binkert
3e5e3e2d28 make all of the turbolaser stuff only compile if ALPHA_TLASER
is defined.

build/SConstruct:
    Default ALPHA_TLASER to false
dev/uart8250.cc:
    fix paths

--HG--
extra : convert_revision : 3616b5b4b9060860a73568a4ed4f1e8eb991938f
2005-06-05 01:24:17 -04:00
Ali Saidi
adce616cfe split uart into urt8250 and uart8530
fix some doxygen comments

SConscript:
    Added split uart files
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/tsunami.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/tsunamireg.h:
    fix doxgyen file comment
dev/uart.cc:
dev/uart.hh:
python/m5/objects/Uart.py:
    split uart into urt8250 and uart8530

--HG--
extra : convert_revision : 2e70aad892a37620d7909017648bca6d7d69d678
2005-06-05 01:22:21 -04:00
Nathan Binkert
b46730c7ec BaseSystem -> System
Make System an object that can be instantiated.  For operating
systems that don't need any OS specific hacks.

python/m5/objects/AlphaConsole.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/Tsunami.py:
    BaseSystem -> System

--HG--
rename : python/m5/objects/BaseSystem.py => python/m5/objects/System.py
extra : convert_revision : e5d12db02abef1b0eda720b50dd2c09cb1ac5232
2005-06-04 14:19:05 -04:00
Steve Reinhardt
af3add2e33 Bug fix & cleanup in config code.
python/m5/config.py:
    Bug fix: code was silently converting between
    incompatible SimObject types as an unintended
    side-effect of the object cloning support.

--HG--
extra : convert_revision : 236f4fe5370f2eddf8af8fab68e2b83dccc34305
2005-06-03 16:21:37 -04:00
Nathan Binkert
0ee75f27b8 Fix-up some config issues
python/m5/config.py:
    Make NetworkBandwidth and MemoryBandwidth work
python/m5/objects/Ethernet.py:
    Make 1Gbps default for ethernet

--HG--
extra : convert_revision : 59e62f7e62624356ae8d7304598617f60667f040
2005-06-02 11:19:01 -04:00
Steve Reinhardt
8031cd93b5 Standardize clock parameter names to 'clock'.
Fix description for Bus clock_ratio (no longer a ratio).
Add Clock param type (generic Frequency or Latency).

cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/beta_cpu/alpha_full_cpu_builder.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/sinic.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
sim/universe.cc:
    Standardize clock parameter names to 'clock'.
    Fix description for Bus clock_ratio (no longer a ratio).
python/m5/config.py:
    Minor tweaks on Frequency/Latency:
    - added new Clock param type to avoid ambiguities
    - factored out init code into getLatency()
    - made RootFrequency *not* a subclass of Frequency so it
    can't be directly assigned to a Frequency paremeter

--HG--
extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506
2005-06-01 21:44:00 -04:00
Steve Reinhardt
3e7f660401 A few more config updates. Works with regression now.
configs/splash2/run.py:
    Update file for new config changes.
python/m5/config.py:
    - isParamContext() not defined any more
    - fix bug with re-assigning vectors over scalars
    and vice versa

--HG--
rename : configs/splash2/run.mpy => configs/splash2/run.py
extra : convert_revision : 2eb28a92f8de327f6dfddd01467c61e759275f6b
2005-06-01 17:08:45 -04:00
Steve Reinhardt
aad02f8088 Major cleanup of python config code.
Special mpy importer is gone; everything is just plain
Python now (funky, but straight-up).
May not completely work yet... generates identical ini
files for many configs/kernel settings, but I have yet
to run it against regressions.  This commit is for my
own convenience and won't be pushed until more testing
is done.

python/m5/__init__.py:
    Get rid of mpy_importer and param_types.
python/m5/config.py:
    Major cleanup.  We now have separate classes and
    instances for SimObjects.  Proxy handling and param
    conversion significantly reorganized.  No explicit
    instantiation step anymore; we can dump an ini file
    straight from the original tree.
    Still needs more/better/truer comments.
test/genini.py:
    Replace LoadMpyFile() with built-in execfile().
    Export __main__.m5_build_env.
python/m5/objects/AlphaConsole.py:
python/m5/objects/AlphaFullCPU.py:
python/m5/objects/AlphaTLB.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/CoherenceProtocol.py:
python/m5/objects/Device.py:
python/m5/objects/DiskImage.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Ide.py:
python/m5/objects/IntrControl.py:
python/m5/objects/MemTest.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/Platform.py:
python/m5/objects/Process.py:
python/m5/objects/Repl.py:
python/m5/objects/Root.py:
python/m5/objects/SimConsole.py:
python/m5/objects/SimpleDisk.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
    Fixes for eliminating mpy_importer, and modified
    handling of frequency/latency params.
    Also renamed parent to Parent.

--HG--
rename : python/m5/objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.mpy => python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.mpy => python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.mpy => python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.mpy => python/m5/objects/BaseCache.py
rename : python/m5/objects/BaseSystem.mpy => python/m5/objects/BaseSystem.py
rename : python/m5/objects/Bus.mpy => python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.mpy => python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.mpy => python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.mpy => python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.mpy => python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.mpy => python/m5/objects/IntrControl.py
rename : python/m5/objects/MemTest.mpy => python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.mpy => python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.mpy => python/m5/objects/Platform.py
rename : python/m5/objects/Process.mpy => python/m5/objects/Process.py
rename : python/m5/objects/Repl.mpy => python/m5/objects/Repl.py
rename : python/m5/objects/Root.mpy => python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.mpy => python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.py
rename : python/m5/objects/Tsunami.mpy => python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.mpy => python/m5/objects/Uart.py
extra : convert_revision : 9dc55103a6f5b40eada4ed181a71a96fae6b0b76
2005-05-29 01:14:50 -04:00
Kevin Lim
e5721ce677 Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/current/m5
--HG--
extra : convert_revision : c403960153ed648e7da7251465ca9350ba10cd27
2005-05-17 14:34:46 -04:00
Steve Reinhardt
16dcebf4c4 Add mem_trace parameter to BaseCache.
python/m5/objects/BaseCache.mpy:
    Add mem_trace parameter.

--HG--
extra : convert_revision : a0bab53fabd7426eee5ca9c845c02a6ac2e1722f
2005-05-13 15:01:42 -04:00