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io_bus is split out into pio_bus and dma_bus so that any device

Browse source 
can specify either independently.

python/m5/objects/Device.py:
    io_bus is split out into pio_bus and dma_bus so that any device
    can specify either independently.
    dma_bus defaults to point to whatever pio_bus uses.

--HG--
extra : convert_revision : d35d5374d0bf592f6b5df465c05203577b8b8763
This commit is contained in:
Nathan Binkert 2005-11-20 16:57:53 -05:00
parent ccae5838fd
commit 12d903a650
22 changed files with 117 additions and 118 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
dev/alpha_console.cc
View file

@ -57,13 +57,13 @@ using namespace std;
AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
System *s, BaseCPU *c, Platform *p,
MemoryController *mmu, Addr a,
HierParams *hier, Bus *bus)
HierParams *hier, Bus *pio_bus)
: PioDevice(name, p), disk(d), console(cons), system(s), cpu(c), addr(a)
{
mmu->add_child(this, RangeSize(addr, size));
if (bus) {
pioInterface = newPioInterface(name + ".pio", hier, bus, this,
if (pio_bus) {
pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
&AlphaConsole::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
}
@ -335,7 +335,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
SimObjectParam<System *> system;
SimObjectParam<BaseCPU *> cpu;
SimObjectParam<Platform *> platform;
SimObjectParam<Bus*> io_bus;
SimObjectParam<Bus*> pio_bus;
Param<Tick> pio_latency;
SimObjectParam<HierParams *> hier;
@ -350,7 +350,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
INIT_PARAM(system, "system object"),
INIT_PARAM(cpu, "Processor"),
INIT_PARAM(platform, "platform"),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
INIT_PARAM(pio_bus, "The IO Bus to attach to"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
@ -359,7 +359,7 @@ END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
CREATE_SIM_OBJECT(AlphaConsole)
{
return new AlphaConsole(getInstanceName(), sim_console, disk,
system, cpu, platform, mmu, addr, hier, io_bus);
system, cpu, platform, mmu, addr, hier, pio_bus);
}
REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)

2
dev/alpha_console.hh
View file

@ -103,7 +103,7 @@ class AlphaConsole : public PioDevice
AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d,
System *s, BaseCPU *c, Platform *platform,
MemoryController *mmu, Addr addr,
HierParams *hier, Bus *bus);
HierParams *hier, Bus *pio_bus);
virtual void startup();

12
dev/baddev.cc
View file

@ -48,13 +48,13 @@
using namespace std;
BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu,
HierParams *hier, Bus *bus, const string &devicename)
HierParams *hier, Bus *pio_bus, const string &devicename)
: PioDevice(name, NULL), addr(a), devname(devicename)
{
mmu->add_child(this, RangeSize(addr, size));
if (bus) {
pioInterface = newPioInterface(name, hier, bus, this,
if (pio_bus) {
pioInterface = newPioInterface(name, hier, pio_bus, this,
&BadDevice::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
}
@ -88,7 +88,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
SimObjectParam<HierParams *> hier;
SimObjectParam<Bus*> io_bus;
SimObjectParam<Bus*> pio_bus;
Param<Tick> pio_latency;
Param<string> devicename;
@ -100,7 +100,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(BadDevice)
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
INIT_PARAM(devicename, "Name of device to error on")
@ -108,7 +108,7 @@ END_INIT_SIM_OBJECT_PARAMS(BadDevice)
CREATE_SIM_OBJECT(BadDevice)
{
return new BadDevice(getInstanceName(), addr, mmu, hier, io_bus,
return new BadDevice(getInstanceName(), addr, mmu, hier, pio_bus,
devicename);
}

27
dev/ide_ctrl.cc
View file

@ -90,20 +90,20 @@ IdeController::IdeController(Params *p)
bm_enabled = false;
memset(cmd_in_progress, 0, sizeof(cmd_in_progress));
pioInterface = NULL;
dmaInterface = NULL;
// create the PIO and DMA interfaces
if (params()->host_bus) {
if (params()->pio_bus) {
pioInterface = newPioInterface(name() + ".pio", params()->hier,
params()->host_bus, this,
params()->pio_bus, this,
&IdeController::cacheAccess);
pioLatency = params()->pio_latency * params()->pio_bus->clockRate;
}
if (params()->dma_bus) {
dmaInterface = new DMAInterface<Bus>(name() + ".dma",
params()->host_bus,
params()->host_bus, 1,
true);
pioLatency = params()->pio_latency * params()->host_bus->clockRate;
} else {
pioInterface = NULL;
dmaInterface = NULL;
params()->dma_bus,
params()->dma_bus, 1, true);
}
// setup the disks attached to controller
@ -719,7 +719,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
Param<uint32_t> pci_bus;
Param<uint32_t> pci_dev;
Param<uint32_t> pci_func;
SimObjectParam<Bus *> io_bus;
SimObjectParam<Bus *> pio_bus;
SimObjectParam<Bus *> dma_bus;
Param<Tick> pio_latency;
SimObjectParam<HierParams *> hier;
@ -736,7 +737,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
INIT_PARAM(pci_bus, "PCI bus ID"),
INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(io_bus, "Host bus to attach to", NULL),
INIT_PARAM(pio_bus, ""),
INIT_PARAM(dma_bus, ""),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
@ -755,7 +757,8 @@ CREATE_SIM_OBJECT(IdeController)
params->functionNum = pci_func;
params->disks = disks;
params->host_bus = io_bus;
params->pio_bus = pio_bus;
params->dma_bus = dma_bus;
params->pio_latency = pio_latency;
params->hier = hier;
return new IdeController(params);

3
dev/ide_ctrl.hh
View file

@ -191,7 +191,8 @@ class IdeController : public PciDev
{
/** Array of disk objects */
std::vector<IdeDisk *> disks;
Bus *host_bus;
Bus *pio_bus;
Bus *dma_bus;
Tick pio_latency;
HierParams *hier;
};

12
dev/isa_fake.cc
View file

@ -47,13 +47,13 @@
using namespace std;
IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu,
HierParams *hier, Bus *bus, Addr size)
HierParams *hier, Bus *pio_bus, Addr size)
: PioDevice(name, NULL), addr(a)
{
mmu->add_child(this, RangeSize(addr, size));
if (bus) {
pioInterface = newPioInterface(name + ".pio", hier, bus, this,
if (pio_bus) {
pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
&IsaFake::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
}
@ -113,7 +113,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
SimObjectParam<Bus*> io_bus;
SimObjectParam<Bus*> pio_bus;
Param<Tick> pio_latency;
SimObjectParam<HierParams *> hier;
Param<Addr> size;
@ -124,7 +124,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake)
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
INIT_PARAM_DFLT(size, "Size of address range", 0x8)
@ -133,7 +133,7 @@ END_INIT_SIM_OBJECT_PARAMS(IsaFake)
CREATE_SIM_OBJECT(IsaFake)
{
return new IsaFake(getInstanceName(), addr, mmu, hier, io_bus, size);
return new IsaFake(getInstanceName(), addr, mmu, hier, pio_bus, size);
}
REGISTER_SIM_OBJECT("IsaFake", IsaFake)

2
dev/isa_fake.hh
View file

@ -58,7 +58,7 @@ class IsaFake : public PioDevice
* @param size number of addresses to respond to
*/
IsaFake(const std::string &name, Addr a, MemoryController *mmu,
HierParams *hier, Bus *bus, Addr size = 0x8);
HierParams *hier, Bus *pio_bus, Addr size = 0x8);
/**
* This read always returns -1.

32
dev/ns_gige.cc
View file

@ -109,13 +109,14 @@ NSGigE::NSGigE(Params *p)
physmem(p->pmem), intrTick(0), cpuPendingIntr(false),
intrEvent(0), interface(0)
{
if (p->header_bus) {
if (p->pio_bus) {
pioInterface = newPioInterface(name() + ".pio", p->hier,
p->header_bus, this,
p->pio_bus, this,
&NSGigE::cacheAccess);
pioLatency = p->pio_latency * p->pio_bus->clockRate;
}
pioLatency = p->pio_latency * p->header_bus->clockRate;
if (p->header_bus) {
if (p->payload_bus)
dmaInterface = new DMAInterface<Bus>(name() + ".dma",
p->header_bus,
@ -126,18 +127,8 @@ NSGigE::NSGigE(Params *p)
p->header_bus,
p->header_bus, 1,
p->dma_no_allocate);
} else if (p->payload_bus) {
pioInterface = newPioInterface(name() + ".pio", p->hier,
p->payload_bus, this,
&NSGigE::cacheAccess);
pioLatency = p->pio_latency * p->payload_bus->clockRate;
dmaInterface = new DMAInterface<Bus>(name() + ".dma",
p->payload_bus,
p->payload_bus, 1,
p->dma_no_allocate);
}
} else if (p->payload_bus)
panic("Must define a header bus if defining a payload bus");
intrDelay = p->intr_delay;
@ -2993,7 +2984,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
Param<uint32_t> pci_func;
SimObjectParam<HierParams *> hier;
SimObjectParam<Bus*> io_bus;
SimObjectParam<Bus*> pio_bus;
SimObjectParam<Bus*> dma_bus;
SimObjectParam<Bus*> payload_bus;
Param<bool> dma_desc_free;
Param<bool> dma_data_free;
@ -3031,7 +3023,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM(hier, "Hierarchy global variables"),
INIT_PARAM(io_bus, "The IO Bus to attach to for headers"),
INIT_PARAM(pio_bus, ""),
INIT_PARAM(dma_bus, ""),
INIT_PARAM(payload_bus, "The IO Bus to attach to for payload"),
INIT_PARAM(dma_desc_free, "DMA of Descriptors is free"),
INIT_PARAM(dma_data_free, "DMA of Data is free"),
@ -3073,7 +3066,8 @@ CREATE_SIM_OBJECT(NSGigE)
params->functionNum = pci_func;
params->hier = hier;
params->header_bus = io_bus;
params->pio_bus = pio_bus;
params->header_bus = dma_bus;
params->payload_bus = payload_bus;
params->dma_desc_free = dma_desc_free;
params->dma_data_free = dma_data_free;

1
dev/ns_gige.hh
View file

@ -368,6 +368,7 @@ class NSGigE : public PciDev
{
PhysicalMemory *pmem;
HierParams *hier;
Bus *pio_bus;
Bus *header_bus;
Bus *payload_bus;
Tick clock;

14
dev/pciconfigall.cc
View file

@ -50,16 +50,16 @@ using namespace std;
PciConfigAll::PciConfigAll(const string &name,
Addr a, MemoryController *mmu,
HierParams *hier, Bus *bus, Tick pio_latency)
HierParams *hier, Bus *pio_bus, Tick pio_latency)
: PioDevice(name, NULL), addr(a)
{
mmu->add_child(this, RangeSize(addr, size));
if (bus) {
pioInterface = newPioInterface(name + ".pio", hier, bus, this,
if (pio_bus) {
pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
&PciConfigAll::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRate;
pioLatency = pio_latency * pio_bus->clockRate;
}
// Make all the pointers to devices null
@ -200,7 +200,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
Param<Addr> mask;
SimObjectParam<Bus*> io_bus;
SimObjectParam<Bus*> pio_bus;
Param<Tick> pio_latency;
SimObjectParam<HierParams *> hier;
@ -211,7 +211,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM(mask, "Address Mask"),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
@ -219,7 +219,7 @@ END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
CREATE_SIM_OBJECT(PciConfigAll)
{
return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus,
return new PciConfigAll(getInstanceName(), addr, mmu, hier, pio_bus,
pio_latency);
}

2
dev/pciconfigall.hh
View file

@ -74,7 +74,7 @@ class PciConfigAll : public PioDevice
* @param bus The bus that this device is attached to
*/
PciConfigAll(const std::string &name, Addr a, MemoryController *mmu,
HierParams *hier, Bus *bus, Tick pio_latency);
HierParams *hier, Bus *pio_bus, Tick pio_latency);
/**

39
dev/sinic.cc
View file

@ -93,31 +93,25 @@ Device::Device(Params *p)
{
reset();
if (p->io_bus) {
pioInterface = newPioInterface(p->name + ".pio", p->hier, p->io_bus,
if (p->pio_bus) {
pioInterface = newPioInterface(p->name + ".pio", p->hier, p->pio_bus,
this, &Device::cacheAccess);
pioLatency = p->pio_latency * p->pio_bus->clockRate;
}
pioLatency = p->pio_latency * p->io_bus->clockRate;
if (p->header_bus) {
if (p->payload_bus)
dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->io_bus,
dmaInterface = new DMAInterface<Bus>(p->name + ".dma",
p->header_bus,
p->payload_bus, 1,
p->dma_no_allocate);
else
dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->io_bus,
p->io_bus, 1,
dmaInterface = new DMAInterface<Bus>(p->name + ".dma",
p->header_bus,
p->header_bus, 1,
p->dma_no_allocate);
} else if (p->payload_bus) {
pioInterface = newPioInterface(p->name + ".pio", p->hier,
p->payload_bus, this,
&Device::cacheAccess);
pioLatency = p->pio_latency * p->payload_bus->clockRate;
dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->payload_bus,
p->payload_bus, 1,
p->dma_no_allocate);
}
} else if (p->payload_bus)
panic("must define a header bus if defining a payload bus");
}
Device::~Device()
@ -1438,7 +1432,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
Param<uint32_t> pci_func;
SimObjectParam<HierParams *> hier;
SimObjectParam<Bus*> io_bus;
SimObjectParam<Bus*> pio_bus;
SimObjectParam<Bus*> dma_bus;
SimObjectParam<Bus*> payload_bus;
Param<Tick> dma_read_delay;
Param<Tick> dma_read_factor;
@ -1479,7 +1474,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM(hier, "Hierarchy global variables"),
INIT_PARAM(io_bus, "The IO Bus to attach to for headers"),
INIT_PARAM(pio_bus, ""),
INIT_PARAM(dma_bus, ""),
INIT_PARAM(payload_bus, "The IO Bus to attach to for payload"),
INIT_PARAM(dma_read_delay, "fixed delay for dma reads"),
INIT_PARAM(dma_read_factor, "multiplier for dma reads"),
@ -1524,7 +1520,8 @@ CREATE_SIM_OBJECT(Device)
params->functionNum = pci_func;
params->hier = hier;
params->io_bus = io_bus;
params->pio_bus = pio_bus;
params->header_bus = dma_bus;
params->payload_bus = payload_bus;
params->dma_read_delay = dma_read_delay;
params->dma_read_factor = dma_read_factor;

3
dev/sinic.hh
View file

@ -316,7 +316,8 @@ class Device : public Base
Tick tx_delay;
Tick rx_delay;
HierParams *hier;
Bus *io_bus;
Bus *pio_bus;
Bus *header_bus;
Bus *payload_bus;
Tick pio_latency;
PhysicalMemory *physmem;

16
dev/tsunami_cchip.cc
View file

@ -49,17 +49,17 @@
using namespace std;
TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
MemoryController *mmu, HierParams *hier, Bus* bus,
Tick pio_latency)
MemoryController *mmu, HierParams *hier,
Bus* pio_bus, Tick pio_latency)
: PioDevice(name, t), addr(a), tsunami(t)
{
mmu->add_child(this, RangeSize(addr, size));
if (bus) {
pioInterface = newPioInterface(name + ".pio", hier, bus, this,
if (pio_bus) {
pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
&TsunamiCChip::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRate;
pioLatency = pio_latency * pio_bus->clockRate;
}
drir = 0;
@ -551,7 +551,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
SimObjectParam<Tsunami *> tsunami;
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
SimObjectParam<Bus*> io_bus;
SimObjectParam<Bus*> pio_bus;
Param<Tick> pio_latency;
SimObjectParam<HierParams *> hier;
@ -562,7 +562,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
INIT_PARAM(tsunami, "Tsunami"),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
@ -571,7 +571,7 @@ END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
CREATE_SIM_OBJECT(TsunamiCChip)
{
return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu, hier,
io_bus, pio_latency);
pio_bus, pio_latency);
}
REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)

2
dev/tsunami_cchip.hh
View file

@ -96,7 +96,7 @@ class TsunamiCChip : public PioDevice
* @param bus The bus that this device is attached to
*/
TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
MemoryController *mmu, HierParams *hier, Bus *bus,
MemoryController *mmu, HierParams *hier, Bus *pio_bus,
Tick pio_latency);
/**

16
dev/tsunami_io.cc
View file

@ -415,18 +415,18 @@ TsunamiIO::PITimer::Counter::CounterEvent::description()
}
TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
Addr a, MemoryController *mmu, HierParams *hier, Bus *bus,
Tick pio_latency, Tick ci)
Addr a, MemoryController *mmu, HierParams *hier,
Bus *pio_bus, Tick pio_latency, Tick ci)
: PioDevice(name, t), addr(a), clockInterval(ci), tsunami(t),
pitimer(name + "pitimer"), rtc(name + ".rtc", t, ci)
{
mmu->add_child(this, RangeSize(addr, size));
if (bus) {
pioInterface = newPioInterface(name + ".pio", hier, bus, this,
if (pio_bus) {
pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
&TsunamiIO::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRate;
pioLatency = pio_latency * pio_bus->clockRate;
}
// set the back pointer from tsunami to myself
@ -688,7 +688,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
Param<time_t> time;
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
SimObjectParam<Bus*> io_bus;
SimObjectParam<Bus*> pio_bus;
Param<Tick> pio_latency;
SimObjectParam<HierParams *> hier;
Param<Tick> frequency;
@ -701,7 +701,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
INIT_PARAM(time, "System time to use (0 for actual time"),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
INIT_PARAM(pio_bus, "The IO Bus to attach to"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
INIT_PARAM(frequency, "clock interrupt frequency")
@ -711,7 +711,7 @@ END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
CREATE_SIM_OBJECT(TsunamiIO)
{
return new TsunamiIO(getInstanceName(), tsunami, time, addr, mmu, hier,
io_bus, pio_latency, frequency);
pio_bus, pio_latency, frequency);
}
REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)

2
dev/tsunami_io.hh
View file

@ -321,7 +321,7 @@ class TsunamiIO : public PioDevice
* @param mmu pointer to the memory controller that sends us events.
*/
TsunamiIO(const std::string &name, Tsunami *t, time_t init_time,
Addr a, MemoryController *mmu, HierParams *hier, Bus *bus,
Addr a, MemoryController *mmu, HierParams *hier, Bus *pio_bus,
Tick pio_latency, Tick ci);
/**

14
dev/tsunami_pchip.cc
View file

@ -50,7 +50,7 @@ using namespace std;
TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
MemoryController *mmu, HierParams *hier,
Bus *bus, Tick pio_latency)
Bus *pio_bus, Tick pio_latency)
: PioDevice(name, t), addr(a), tsunami(t)
{
mmu->add_child(this, RangeSize(addr, size));
@ -61,11 +61,11 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
tba[i] = 0;
}
if (bus) {
pioInterface = newPioInterface(name + ".pio", hier, bus, this,
if (pio_bus) {
pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
&TsunamiPChip::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRate;
pioLatency = pio_latency * pio_bus->clockRate;
}
@ -360,7 +360,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
SimObjectParam<Tsunami *> tsunami;
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
SimObjectParam<Bus*> io_bus;
SimObjectParam<Bus*> pio_bus;
Param<Tick> pio_latency;
SimObjectParam<HierParams *> hier;
@ -371,7 +371,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
INIT_PARAM(tsunami, "Tsunami"),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
@ -380,7 +380,7 @@ END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
CREATE_SIM_OBJECT(TsunamiPChip)
{
return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu, hier,
io_bus, pio_latency);
pio_bus, pio_latency);
}
REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)

2
dev/tsunami_pchip.hh
View file

@ -82,7 +82,7 @@ class TsunamiPChip : public PioDevice
* @param bus The bus that this device is attached to
*/
TsunamiPChip(const std::string &name, Tsunami *t, Addr a,
MemoryController *mmu, HierParams *hier, Bus *bus,
MemoryController *mmu, HierParams *hier, Bus *pio_bus,
Tick pio_latency);
/**

15
dev/uart8250.cc
View file

@ -98,9 +98,10 @@ Uart8250::IntrEvent::scheduleIntr()
}
Uart8250::Uart8250(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
Addr s, HierParams *hier, Bus *bus, Tick pio_latency, Platform *p)
: Uart(name, c, mmu, a, s, hier, bus, pio_latency, p),
Uart8250::Uart8250(const string &name, SimConsole *c, MemoryController *mmu,
Addr a, Addr s, HierParams *hier, Bus *pio_bus,
Tick pio_latency, Platform *p)
: Uart(name, c, mmu, a, s, hier, pio_bus, pio_latency, p),
txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
{
IER = 0;
@ -318,7 +319,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
SimObjectParam<Platform *> platform;
Param<Addr> addr;
Param<Addr> size;
SimObjectParam<Bus*> io_bus;
SimObjectParam<Bus*> pio_bus;
Param<Tick> pio_latency;
SimObjectParam<HierParams *> hier;
@ -332,7 +333,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
INIT_PARAM(platform, "Pointer to platfrom"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM_DFLT(size, "Device size", 0x8),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
INIT_PARAM(pio_bus, ""),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
@ -340,8 +341,8 @@ END_INIT_SIM_OBJECT_PARAMS(Uart8250)
CREATE_SIM_OBJECT(Uart8250)
{
return new Uart8250(getInstanceName(), console, mmu, addr, size, hier, io_bus,
pio_latency, platform);
return new Uart8250(getInstanceName(), console, mmu, addr, size, hier,
pio_bus, pio_latency, platform);
}
REGISTER_SIM_OBJECT("Uart8250", Uart8250)

2
dev/uart8250.hh
View file

@ -79,7 +79,7 @@ class Uart8250 : public Uart
public:
Uart8250(const std::string &name, SimConsole *c, MemoryController *mmu,
Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency,
Platform *p);
virtual Fault read(MemReqPtr &req, uint8_t *data);

5
python/m5/objects/Device.py
View file

@ -16,12 +16,13 @@ class FooPioDevice(FunctionalMemory):
abstract = True
addr = Param.Addr("Device Address")
mmu = Param.MemoryController(Parent.any, "Memory Controller")
io_bus = Param.Bus(NULL, "The IO Bus to attach to")
pio_bus = Param.Bus(NULL, "Bus to attach to for PIO")
pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
class FooDmaDevice(FooPioDevice):
type = 'DmaDevice'
abstract = True
dma_bus = Param.Bus(Self.pio_bus, "Bus to attach to for DMA")
class PioDevice(FooPioDevice):
type = 'PioDevice'
@ -31,4 +32,4 @@ class PioDevice(FooPioDevice):
class DmaDevice(PioDevice):
type = 'DmaDevice'
abstract = True
dma_bus = Param.Bus(Self.pio_bus, "Bus to attach to for DMA")