objects/Root.mpy:
Fake the param context stuff for now.
sim/param.cc:
Make empty vector enums work
sim/serialize.cc:
serialize_dir is always valid
--HG--
extra : convert_revision : c46373f0f4c70e6a2f01a81c0fa6bacab72d4c4f
util/pbs/send.py:
- add a -d to set the job root directory allowing one to run
send.py from anywhere.
- specify full paths to files instead of relative paths to make -d
work and to allow ssh qsub to work again.
- make the Link directory only copy links that point to regular files.
--HG--
extra : convert_revision : dd330cee08b97c5d72c3d58ef123f83ac7ccede7
base/str.cc:
base/str.hh:
Add a couple functions that allow you to split a string at
the first or last instance of a delimiter.
--HG--
extra : convert_revision : 2af22639e1b67ac61577c00475a555841a56f902
Increase the default number of CSHR's, we should really fix this or make it a parameter
Use a setBlocked call to tell the bus it should block
New technique for sampling and switchover:
1) Sampler switchover event happens
2) All cpus in the current phase of sampling associated with this sampler are signaled to switchover
3) Each cpu drains it's pipe of things being executed (stops fetching and waits for empty pipe)
4) Once the pipe is empty the cpu calls back to the sampler to signal it has finished, and moves into the switchedout state (continues not to fetch)
5) The sampler collects all the signals, once all cpus are drained it calls the new cpu's in the next phase to takeover from the correct cpu
6) The statistics are reset and the next switchover time is calculated from this point
cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
Reconfigure the way the sampling switchover works
cpu/pc_event.cc:
More debugging information on kernel panic's
kern/linux/linux_system.cc:
More debug info for Kernel Die events
kern/linux/linux_system.hh:
More debug info for kernel die events
--HG--
extra : convert_revision : 61cc42e43ba738705aa1f1d167b65d4d6dee51ae
Fix up configuration scrupts to have better support for
running on the simulation pool.
--HG--
extra : convert_revision : 0178c8600b193d6c0ca69163fb735a7fa0e70782
dev/tsunami_cchip.cc:
add a fake register to tsunami that we can do 32bit reads to.
Warn on access.
--HG--
extra : convert_revision : d87860f3b527528151c23431556039bca6e12945
util/tracediff:
Fix bug (used += instead of .= for string concatenation in Perl...
wrong language!).
Also updated for new config (s/Universe/root/).
--HG--
extra : convert_revision : 0db3f22794037dc51cc29f78a75bd22012a8ecd9
address calculation and memory access portions separately.
Not currently used by any CPU models, but Kevin says he needs this.
Also clean up handling of execution tracing for memory accesses
(move it all into isa_desc and out of CPU models).
Got rid of some ancient unused code too.
arch/alpha/isa_desc:
Add execute() methods to EAComp and MemAcc portions of memory
access instructions, to allow CPU models to execute the effective
address calculation and memory access portions separately.
Requires the execution context to remember the effective address
across the two invocations. Added setEA() and getEA() methods to
execution context to support this. A model that does not use the
split execution model can panic if these methods are called.
Also added hook to call traceData->setAddr() after EA computation
on any load or store operation.
arch/isa_parser.py:
Call traceData->setData() on memory writes (stores).
cpu/simple_cpu/simple_cpu.cc:
Get rid of unused code.
cpu/simple_cpu/simple_cpu.hh:
Add (non-functional) setEA() and getEA() methods for new
split memory access execution support.
--HG--
extra : convert_revision : bc2d2c758c4ca753812b9fa81f21038e55929ff0
get rid of the alias for true to True and false to False to keep
consistent python syntax.
util/stats/info.py:
Fix typo
--HG--
extra : convert_revision : e69588a8de52424e043315e70008ca3a3ede7d5b
dev/simconsole.cc:
sim/universe.cc:
isValid isn't compatible with new python stuff, so whack it.
--HG--
extra : convert_revision : 0c50038769a558650479c51122a8be5d92e7d9c4
objects/AlphaConsole.mpy:
objects/AlphaTLB.mpy:
objects/BadDevice.mpy:
objects/BaseCPU.mpy:
objects/BaseCache.mpy:
objects/BaseSystem.mpy:
objects/Bus.mpy:
objects/CoherenceProtocol.mpy:
objects/Device.mpy:
objects/DiskImage.mpy:
objects/Ethernet.mpy:
objects/Ide.mpy:
objects/IntrControl.mpy:
objects/MemTest.mpy:
objects/Pci.mpy:
objects/PhysicalMemory.mpy:
objects/Platform.mpy:
objects/Process.mpy:
objects/Repl.mpy:
objects/Root.mpy:
objects/SimConsole.mpy:
objects/SimpleDisk.mpy:
objects/Tsunami.mpy:
objects/Uart.mpy:
simobj now requires a type= line if it is actually intended
to be a type
sim/pyconfig/SConscript:
keep track of the filename of embedded files for better
error messages.
sim/pyconfig/m5config.py:
Add support for the trickery done with the compiler to get the
simobj language feature added to the importer.
fix the bug that gave objects the wrong name in error messages.
test/genini.py:
Globals have been fixed and use execfile
--HG--
extra : convert_revision : b74495fd6f3479a87ecea7f1234ebb6731279b2b
objects/BaseCache.mpy:
add all the Split parameters to the BaseCache simobj.
--HG--
extra : convert_revision : 4fcba3ce730f730ca8628ac7f4aa0fb9476474ab
all but tlaser_node.cc dependence on tlaserreg.h
dev/tsunami_io.cc:
dev/tsunamireg.h:
removed tlaserreg.h
--HG--
extra : convert_revision : 148a5d79530e5ed721a49279f684a48041deed2b
base/stats/events.cc:
cast this to an unsigned long long to make the compiler happy
on 64-bit platforms.
--HG--
extra : convert_revision : e893d21bb228cbfb0c23adb7c4eeb1f62209ca1c
dev/pktfifo.cc:
Make it so that we don't unserialize the size of the fifo, clobering the fact that we were trying to make it bigger, and leading to a misleading config.out that states the un-overwritten max_size.
Perhaps this should instead be a panic if the size (amount that was serialized) is bigger than the maxsize that was assigned by the configuration file.
--HG--
extra : convert_revision : d4b0527bfd7a584554ddc87c9b2103f7a3a72332
arch/alpha/pseudo_inst.cc:
rename the context for consistency.
sim/pyconfig/m5config.py:
Add a ParamContext class so that param contexts work with
the new config stuff.
--HG--
extra : convert_revision : 3a6b583a25c86237baca7a2b4eccc9d12f86a384
cleaned up stability code and wrote some better help for stats.py
fixed sample bug in info.py
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/sinic.cc:
dev/sinic.hh:
add total bandwidth/packets/bytes stats
util/stats/info.py:
fixed samples bug
util/stats/stats.py:
cleaned up stability code and wrote a bit better help
--HG--
extra : convert_revision : cae06f4fac744d7a51ee0909f21f03509151ea8f
