succesfully but there are some minor quirks to iron out. Who would've known a DELAY SLOT introduces that much complexity?! arrgh!
Anyways, a lot of this stuff had to do with my project at MIPS and me needing to know how I was going to get this working for the MIPS
ISA. So I figured I would try to touch it up and throw it in here (I hate to introduce non-completely working components... )
src/arch/alpha/isa/mem.isa:
spacing
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
Gabe really authored this
src/arch/mips/isa/decoder.isa:
add StoreConditional Flag to instruction
src/arch/mips/isa/formats/basic.isa:
Steven really did this file
src/arch/mips/isa/formats/branch.isa:
fix bug for uncond/cond control
src/arch/mips/isa/formats/mem.isa:
Adjust O3CPU memory access to use new memory model interface.
src/arch/mips/isa/formats/util.isa:
update LoadStoreBase template
src/arch/mips/isa_traits.cc:
update SERIALIZE partially
src/arch/mips/process.cc:
src/arch/mips/process.hh:
no need for this for NOW. ASID/Virtual addressing handles it
src/arch/mips/regfile/misc_regfile.hh:
add in clear() function and comments for future usage of special misc. regs
src/cpu/base_dyn_inst.hh:
add in nextNPC variable and supporting functions.
add isCondDelaySlot function
Update predTaken and mispredicted functions
src/cpu/base_dyn_inst_impl.hh:
init nextNPC
src/cpu/o3/SConscript:
add MIPS files to compile
src/cpu/o3/alpha/thread_context.hh:
no need for my name on this file
src/cpu/o3/bpred_unit_impl.hh:
Update RAS appropriately for MIPS
src/cpu/o3/comm.hh:
add some extra communication variables to aid in handling the
delay slots
src/cpu/o3/commit.hh:
minor name fix for nextNPC functions.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
Fix necessary variables and functions for squashes with delay slots
src/cpu/o3/cpu.cc:
Update function interface ...
adjust removeInstsNotInROB function to recognize delay slots insts
src/cpu/o3/cpu.hh:
update removeInstsNotInROB
src/cpu/o3/decode.hh:
declare necessary variables for handling delay slot
src/cpu/o3/dyn_inst.hh:
Add in MipsDynInst
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/rename.hh:
declare necessary variables and adjust functions for handling delay slot
src/cpu/o3/inst_queue.hh:
src/cpu/simple/base.cc:
no need for my name here
src/cpu/o3/isa_specific.hh:
add in MIPS files
src/cpu/o3/scoreboard.hh:
dont include alpha specific isa traits!
src/cpu/o3/thread_context.hh:
no need for my name here, i just rearranged where the file goes
src/cpu/static_inst.hh:
add isCondDelaySlot function
src/cpu/o3/mips/cpu.cc:
src/cpu/o3/mips/cpu.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/mips/dyn_inst.cc:
src/cpu/o3/mips/dyn_inst.hh:
src/cpu/o3/mips/dyn_inst_impl.hh:
src/cpu/o3/mips/impl.hh:
src/cpu/o3/mips/params.hh:
src/cpu/o3/mips/thread_context.cc:
src/cpu/o3/mips/thread_context.hh:
MIPS file for O3CPU...mirrors ALPHA definition
--HG--
extra : convert_revision : 9bb199b4085903e49ffd5a4c8ac44d11460d988c
src/cpu/checker/cpu.hh:
Don't count checker's instructions towards total instructions committed.
src/python/m5/objects/Root.py:
Set default clock to 1 THz.
--HG--
extra : convert_revision : 0b5eaa197c860c361a3b00087e45ddc249ff1918
Right now only non-SMT SE regression tests have been added back in. The rest are pending getting SMT working, and consolidating the FS configuration files.
Eventually support for different OSs can be added so you can specify which versions of the binary you want to run from one config file.
Note: mp-test1 doesn't have any reference stats because MP mode doesn't currently work. The test itself should probably work once the code is fixed.
SConstruct:
Updates to allow for regression tests to work via the command line "scons build/ALPHA_SE/test/debug/quick" and such once again.
src/cpu/SConscript:
Keep a list of SMT supporting CPUs so that the regression tests can easily specify which CPUs to use if they are SMT only.
--HG--
extra : convert_revision : 34e6286150aae8f316ae694f6c00be8f510522f2
src/cpu/o3/lsq_unit.hh:
LSQ needs to decrement the WB counter if the load is going to be replayed.
src/cpu/o3/lsq_unit_impl.hh:
LSQ needs to decrement the WB counter if the load is squashed.
--HG--
extra : convert_revision : 20a10baf0d6ab46065e561ddba231251865ebdbd
src/arch/SConscript:
Fixes for including the CheckerCPU if it's specified via command line. Previously the env variable was actually being modified.
src/cpu/SConscript:
Copy the CPU_MODELS from the env, don't create a proxy to it.
--HG--
extra : convert_revision : 7d069bd93a6834ccaa1c378b2bc76dce76745c19
suspend context will now take the thread off the activeThread list.
src/arch/mips/isa_traits.cc:
add in copy MiscRegs unimplemented function
--HG--
extra : convert_revision : 3ed5320b3786f84d4bb242e3a32b6f415339c3ba
src/cpu/o3/lsq.hh:
Update to have LSQ work with only one dcache port for all LSQ Units. LSQ has the dcache port, and the LSQ Units must tell the LSQ if the cache has become blocked.
src/cpu/o3/lsq_impl.hh:
Updates to have the LSQ work with only one dcache port for all LSQUnits.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
Update for LSQ to create dcache port instead of LSQUnits. Now LSQUnits are given the dcache port from the LSQ, and also must check the LSQ if the cache is blocked prior to accessing the cache.
--HG--
extra : convert_revision : 2708adbf323f4e7647dc0c1e31ef5bb4596b89f8
States are now running, draining, or drained. memory state information moved into system object
system parameter is not fs only for cpus
Implement drain() support in devices
Update for drain() call that returns number of times drain_event->process() will be called
Break O3 CPU! No sense in putting in a hack change that kevin is going to remove in a few minutes i imagine
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
Since se mode has a system, allow access to it
Verify that the atomic cpu is connected to an atomic system on resume
src/cpu/simple/base.cc:
Since se mode has a system, allow access to it
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Update for new drain() call that returns number of times drain_event->process() will be called and memory state being moved into the system
Since se mode has a system, allow access to it
Verify that the timing cpu is connected to an timing system on resume
src/dev/ide_disk.cc:
src/dev/io_device.cc:
src/dev/io_device.hh:
src/dev/ns_gige.cc:
src/dev/ns_gige.hh:
src/dev/pcidev.cc:
src/dev/pcidev.hh:
src/dev/sinic.cc:
src/dev/sinic.hh:
Implement drain() support in devices
src/python/m5/config.py:
Allow drain to return number of times drain_event->process() will be called. Normally 0 or 1 but things like O3 cpu or devices with multiple ports may want to call it many times
src/python/m5/objects/BaseCPU.py:
move system parameter out of fs to everyone
src/sim/sim_object.cc:
src/sim/sim_object.hh:
States are now running, draining, or drained. memory state information moved into system object
src/sim/system.cc:
src/sim/system.hh:
memory mode information now contained in system object
--HG--
extra : convert_revision : 1389c77e66ee6d9710bf77b4306fb47e107b21cf
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
configs/test/test.py:
Hand merge.
--HG--
extra : convert_revision : e3fce9cf50a65a9400cd3ec887b13e4765274ec2
src/cpu/o3/commit_impl.hh:
Always set instruction. This is necessary for serialization as the instruction is also serialized.
src/cpu/o3/cpu.cc:
Change serialization so it matches other CPU's output. Also fix up some indexing.
--HG--
extra : convert_revision : 52f6e183132d177bed6e29dd7cf0c10aed6d8534
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
src/cpu/o3/fetch_impl.hh:
Hand merge.
--HG--
extra : convert_revision : 820dab2bc921cbadecaca51cd069327f984f5c74
Now hello world works with 2 levels of cache with O3 CPU(multiple outstanding requests).
src/cpu/o3/fetch_impl.hh:
Fix ordering issue with squashed Icache Fetches and Static data in packet.
--HG--
extra : convert_revision : a6adb87540b007ead0b4982cb3f31da8199fb5ca
src/cpu/SConscript:
Change the error message to be slightly nicer.
src/cpu/o3/commit.hh:
Remove old code.
src/cpu/o3/commit_impl.hh:
Remove old unused code.
--HG--
extra : convert_revision : 48aa430e1f3554007dd5e4f3d9e89b5e4f124390
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision : 9098d989832e2a5818b80771e3c02170c5c8cd5b
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/python/m5/objects/OzoneCPU.py:
Support Ron's recent port changes.
src/cpu/ozone/lw_back_end_impl.hh:
Support Ron's recent port changes. Also support handling faults in SE.
--HG--
extra : convert_revision : aa1ba5111b70199c052da3e13bae605525a69891
src/cpu/checker/cpu.hh:
Now that BaseCPU is a MemObject, the checker must define this function.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_unit.hh:
Implement getPort function so the connector can connect the ports properly.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
The connector handles connecting the ports now.
src/python/m5/objects/O3CPU.py:
Add ports to the parameters.
--HG--
extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision : f97469b7d19c82deb3d068f80546d729757c25e3
Still, there is a problem with the LSQ and indexing out of range in the buffer.
I havent nailed down the fix yet, but it's coming ...
src/cpu/o3/commit_impl.hh:
add space to DPRINT
src/cpu/o3/cpu.cc:
add newline to DPRINT
src/cpu/o3/rob.hh:
src/cpu/o3/rob_impl.hh:
Each thread needs it's own squashedSeqNum for the case where they are both squashing at the same time and they dont
write over each other's squash number.
--HG--
extra : convert_revision : 2155421a8b5b20e4544eea3d3c53d3e715465fa6
src/cpu/o3/cpu.cc:
Fix up keeping proper state when switched out and drained.
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Keep track of the event we use to schedule fetch initially and upon resume. We may have to cancel the event if the CPU is switched out.
--HG--
extra : convert_revision : 60a2a1bd2cdc67bd53ca4a67aa77166c826a4c8c
configs/test/test.py:
Update to use new cpu getPort functionality
src/cpu/base.cc:
Make cpu's a memObject to expose getPort interface
src/cpu/base.hh:
Make cpu's a memObject to export getPort interface
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Now use the connector via getPort interface
src/mem/cache/base_cache.cc:
Make sure the cache recognizes all port names
--HG--
extra : convert_revision : dbfefa978ec755bc8aa6f962ae158acf32dafe61
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision : 90717b492139428e0c48be35a6bda45960c61086
Major thing was to not execute commit if there are no active threads in CPU.
src/cpu/o3/alpha/thread_context.hh:
call deallocate instead of deallocateContext
src/cpu/o3/commit_impl.hh:
dont run commit stage if there are no instructions
src/cpu/o3/cpu.cc:
add deallocate event, deactivateThread function, and edit deallocateContext.
src/cpu/o3/cpu.hh:
add deallocate event and add optional delay to deallocateContext
src/cpu/o3/thread_context.hh:
optional delay for deallocate
src/cpu/o3/thread_context_impl.hh:
edit DPRINTFs to say Thread Context instead of Alpha TC
src/cpu/thread_context.hh:
optional delay
src/sim/syscall_emul.hh:
name stuff
--HG--
extra : convert_revision : f4033e1f66b3043d30ad98dcc70d8b193dea70b6
src/cpu/o3/commit_impl.hh:
Fix to clear drainPending variable on call to resume.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
Support serializing and unserializing in the O3 CPU.
src/cpu/o3/lsq_impl.hh:
Be sure to say we have no stores to write back if the active thread list is empty.
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
Slightly change how SimpleThread is used to copy from other ThreadContexts.
--HG--
extra : convert_revision : 92a5109b3783a989d5b451036061ef82c56d3121
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/rename.hh:
src/cpu/o3/rename_impl.hh:
Return a value so that the CPU can instantly return from draining if the pipeline is already drained.
src/cpu/o3/cpu.cc:
Use values returned from pipeline stages so that the CPU can instantly return from draining if the pipeline is already drained.
--HG--
extra : convert_revision : d8ef6b811644ea67c8b40c4719273fa224105811
src/arch/alpha/regfile.hh:
Define serialize/unserialize functions on MiscRegFile itself.
src/cpu/o3/regfile.hh:
Remove old commented code.
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
Push common serialization code to ThreadState level. Also allow the SimpleThread to be used for checkpointing by other models.
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
Move common serialization code into ThreadState.
--HG--
extra : convert_revision : ef64ef515355437439af967eda2e610e8c1b658b
Still need
1) detailed CPU (blocking ability in cache)
1a) Multiple outstanding requests (need to keep track of times for events)
2)Multi-level support
3)MP coherece support
4)LL/SC support
5)Functional path needs to be correctly implemented (temporarily works without multiple outstanding requests (simple cpu))
src/cpu/simple/timing.cc:
Temp hack because timing cpu doesn't export ports properly so single I/D cache communicates only through the Icache port.
src/mem/cache/base_cache.cc:
Handle marking MSHR's in service
Add support for getting CSHR's
src/mem/cache/base_cache.hh:
Make these functions visible at the base cache level
src/mem/cache/cache.hh:
make the functions virtual
src/mem/cache/cache_impl.hh:
Rename the function to make sense
src/mem/packet.hh:
Accidentally clearing the needsResponse field when sending a response back.
--HG--
extra : convert_revision : 2325d4e0b77e470fa9da91490317dc8ed88b17e2
src/cpu/simple/timing.cc:
Update for changed return values.
src/python/m5/__init__.py:
Loop in order to make sure all objects are really drained. Objects may become undrained as other objects become drained (e.g. a bus-bridge has a packet, while a bus is empty, and the first drain() will cause the bus-bridge to give the packet to the bus).
The only case we know every object is actually drained is if they all return immediately that they are drained.
--HG--
extra : convert_revision : 80057a1d6d30381bd0b67b23549bd202f447c5cb
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision : 2f08ea52ef54118d42aa590c0d86aa0cc7988713
src/cpu/cpu_models.py:
Use O3DynInst
src/cpu/o3/dyn_inst.hh:
declare O3DynInst here based off of ISA ... this must be updated for each ISA.
src/cpu/static_inst.hh:
take out O3 forward declarations here and include header file to keep this file clean
--HG--
extra : convert_revision : 0d65463479c3cfc2d1154935b1032dae32c5efd0
src/arch/mips/isa/formats/fp.isa:
Adjust for newmem
src/cpu/cpu_models.py:
Use O3DynInst instead of convoluted way
src/cpu/o3/alpha/impl.hh:
take out O3DynInst typedef here ...
src/cpu/o3/cpu.cc:
open up the SMT functions in the O3CPU
src/cpu/static_inst.hh:
Add O3DynInst
src/cpu/o3/dyn_inst.hh:
Use to get ISA-specific O3DynInst
--HG--
extra : convert_revision : 3713187ead93e336e80889e23a1f1d2f36d664fe
