Steve Reinhardt
13a15c55a4
stats: update stats for previous cset
...
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
2010-09-21 23:07:35 -07:00
Steve Reinhardt
9e45ada171
stats: update stats for preceding coherence changes
...
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
2010-09-09 14:40:19 -04:00
Steve Reinhardt
0f8b5afd7a
tests: update reference config.ini files for previous cset
...
Rename 'responder_set' to 'use_default_range'.
2010-08-17 05:06:22 -07:00
Gabe Black
8b0c83008e
X86: Update stats for the updated auxilliary vectors.
2010-05-03 00:45:01 -07:00
Lisa Hsu
ee20a7c0bd
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 10:08:41 -08:00
Nathan Binkert
14b5169750
tests: update statistics for change caused by vsyscall support in x86
...
Caused by a slight change in memory layout.
2009-11-08 20:15:23 -08:00
Steve Reinhardt
7b40c36fbd
Update stats for new single bad-address responder.
...
Mostly just config.ini updates, though the different response
latency for bad addresses caused very minor timing changes
in the O3 Linux boot tests.
2009-04-22 01:55:52 -04:00
Nathan Binkert
374ba9bae3
tests: update tests for TLB unification
2009-04-08 22:21:30 -07:00
Steve Reinhardt
89ea323250
Update stats for new prefetching fixes.
...
Prefetching is not enabled in any of our regressions, so no significant
stat values have changed, but zero-valued prefetch stats no longer
show up when prefetching is disabled so there are noticable changes
in the reference stat files anyway.
2009-02-16 12:09:45 -05:00
Gabe Black
d824af340e
X86: Update stats now that the micropc isn't always reset on faults.
2009-02-01 17:02:16 -08:00
Gabe Black
c981b7ed50
X86: Add x86 reference output for the timing CPU.
2008-11-09 21:57:15 -08:00
