Commit graph

470 commits

Author SHA1 Message Date
Andreas Hansson
6cf9f182f6 MEM: Fix residual bus ports and make them master/slave
This patch cleans up a number of remaining uses of bus.port which
is now split into bus.master and bus.slave. The only non-trivial change
is the memtest where the level building now has to be aware of the role
of the ports used in the previous level.
2012-02-14 14:15:30 -05:00
Andreas Hansson
ac91f90145 Script: Fix the scripts that use the num_cpus cache parameter
This patch merely removes the use of the num_cpus cache parameter
which no longer exists after the introduction of the masterIds. The
affected scripts fail when trying to set the parameter. Note that this
patch does not update the regression stats.
2012-02-14 12:11:18 -05:00
Andreas Hansson
00978170f3 MEM: Fix master/slave ports in Ruby and non-regression scripts
This patch brings the Ruby and other scripts up to date with the
introduction of the master/slave ports.
2012-02-14 03:41:53 -05:00
Andreas Hansson
5a9a743cfc MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave
and enforces a binding of master to slave. Conceptually, a master (such
as a CPU or DMA port) issues requests, and receives responses, and
conversely, a slave (such as a memory or a PIO device) receives
requests and sends back responses. Currently there is no
differentiation between coherent and non-coherent masters and slaves.

The classification as master/slave also involves splitting the dual
role port of the bus into a master and slave port and updating all the
system assembly scripts to use the appropriate port. Similarly, the
interrupt devices have to have their int_port split into a master and
slave port. The intdev and its children have minimal changes to
facilitate the extra port.

Note that this patch does not enforce any port typing in the C++
world, it merely ensures that the Python objects have a notion of the
port roles and are connected in an appropriate manner. This check is
carried when two ports are connected, e.g. bus.master =
memory.port. The following patches will make use of the
classifications and specialise the C++ ports into masters and slaves.
2012-02-13 06:43:09 -05:00
Ali Saidi
67f16a48fb configs: fix minor config bugs posted on the mailing list 2012-02-12 17:18:53 -06:00
Mrinmoy Ghosh
7e104a1af2 prefetcher: Make prefetcher a sim object instead of it being a parameter on cache 2012-02-12 16:07:38 -06:00
Gabe Black
6cae538ce9 X86: Rename the bridge which allows commnication back to the local APICs.
There was a collision with a name used in fs.py, and that causes that script
not to work when used with x86.
2012-02-05 01:37:40 -08:00
Ali Saidi
0a26883296 configs: More fixes for the memory system updates 2012-02-01 09:48:28 -08:00
Gabe Black
e88165a431 Merge with main repository. 2012-01-30 21:07:57 -08:00
Andreas Hansson
ade53def92 Ruby: Connect system port in Ruby network test
This patch moves the connection of the system port to create_system in
Ruby.py. Thereby it allows the failing Ruby test (and other Ruby
systems) to run again.
2012-01-30 09:37:06 -05:00
Gabe Black
39f314cc15 Yet another merge with the main repository.
--HG--
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/x86/linux/o3-timing/simout => tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
rename : tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini => tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/simout => tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simout => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
2012-01-29 03:27:15 -08:00
Nilay Vaish
ce336fae6a Config: Enable O3 CPU and Ruby in FS mode 2012-01-28 19:33:37 -06:00
Gabe Black
d7f71bf424 SE/FS: Get rid of FULL_SYSTEM in the configs directory 2012-01-28 07:24:50 -08:00
Gabe Black
ec20ee2f7c SE/FS: Make SE vs. FS mode a runtime parameter. 2012-01-28 07:24:34 -08:00
Ronald Dreslinski
38ee552798 configs: actually add ARMv7a-like cpu/cache file 2012-01-26 16:44:43 -05:00
Ronald Dreslinski
fc7cf40de6 configs: A more realistic configuration of an ARM-like processor 2012-01-26 14:53:48 -05:00
Andreas Hansson
53c130bf2f MEM: Fix fs.py by specifying the range size rather than end
This patch fixes the currently broken fs.py by specifying the size of
the bridge range rather than the end address. This effectively
subtracts one when determining the address range for the IO bridge
(from IO bus to membus), and thus avoids the overlapping ranges.
2012-01-25 12:44:43 -05:00
Nilay Vaish
24c2300998 Config: Enable using O3 CPU and Ruby in SE mode 2012-01-23 11:33:52 -06:00
Nilay Vaish
63563c9df2 O3, Ruby: Forward invalidations from Ruby to O3 CPU
This patch implements the functionality for forwarding invalidations and
replacements from the L1 cache of the Ruby memory system to the O3 CPU. The
implementation adds a list of ports to RubyPort. Whenever a replacement or an
invalidation is performed, the L1 cache forwards this to all the ports, which
is the LSQ in case of the O3 CPU.
2012-01-23 11:07:14 -06:00
Andreas Hansson
55cf3f4ac1 MEM: Removing the default port peer from Python ports
In preparation for the introduction of Master and Slave ports, this
patch removes the default port parameter in the Python port and thus
forces the argument list of the Port to contain only the
description. The drawback at this point is that the config port and
dma port of PCI and DMA devices have to be connected explicitly. This
is key for future diversification as the pio and config port are
slaves, but the dma port is a master.
2012-01-17 12:55:09 -06:00
Andreas Hansson
2208ea049f MEM: Make the bus bridge unidirectional and fixed address range
This patch makes the bus bridge uni-directional and specialises the
bus ports to be a master port and a slave port. This greatly
simplifies the assumptions on both sides as either port only has to
deal with requests or responses. The following patches introduce the
notion of master and slave ports, and would not be possible without
this split of responsibilities.

In making the bridge unidirectional, the address range mechanism of
the bridge is also changed. For the cases where communication is
taking place both ways, an additional bridge is needed. This causes
issues with the existing mechanism, as the busses cannot determine
when to stop iterating the address updates from the two bridges. To
avoid this issue, and also greatly simplify the specification, the
bridge now has a fixed set of address ranges, specified at creation
time.
2012-01-17 12:55:09 -06:00
Andreas Hansson
f85286b3de MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort      > PortProxy
TranslatingPort     > SETranslatingPortProxy
VirtualPort         > FSTranslatingPortProxy

--HG--
rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-17 12:55:08 -06:00
Nilay Vaish
c57dc3ffcb Ruby: Use map option for selecting b/w sparse and memory vector 2012-01-11 13:53:38 -06:00
Nilay Vaish
03229f2575 Config: Add support for restoring using a timing CPU
Currently there is an assumption that restoration from a checkpoint will
happen by first restoring to an atomic CPU and then switching to a timing
CPU. This patch adds support for directly restoring to a timing CPU. It
adds a new option '--restore-with-cpu' which is used to specify the type
of CPU to which the checkpoint should be restored to. It defaults to
'atomic' which was the case before.
2012-01-11 13:50:18 -06:00
Nilay Vaish
bd739a75b9 Ruby: remove the files related to the tracer
The Ruby Tracer is out of date with the changes that are being carried
out to support checkpointing. Hence, it needs to be removed.
2012-01-10 18:35:45 -06:00
Nilay Vaish
e4b447754e Config: Remove short option string for cpu type 2012-01-10 06:35:40 -06:00
Ali Saidi
bcb71963eb ARM: Add support for running multiple systems 2012-01-09 18:08:20 -06:00
Ali Saidi
80a6907927 ARM: Add support for initparam m5 op 2012-01-09 18:08:20 -06:00
Ali Saidi
6a6d888ab4 cpu2000: Add missing art benchmark to all 2012-01-09 18:08:20 -06:00
Nilay Vaish
10c2e8ae9a Ruby Cache: Add param for marking caches as instruction only 2012-01-07 07:38:53 -06:00
Nilay Vaish
a88ec980a4 Config: Add an option of type 'choice' for cpu type
This patch adds a new option for cpu type. This option is of type 'choice'
which is similar to a C++ enum, except that it takes string values as
possible choices. Following options are being removed -- detailed, timing,
inorder.

--HG--
extra : rebase_source : 58885e2e8a88b6af8e6ff884a5922059dbb1a6cb
2012-01-05 11:04:25 -06:00
Anthony Gutierrez
19e65a6502 ARM: Update config files for Android/BBench images available on website.
--HG--
extra : rebase_source : ca98021c3f96422374fbd4500da312a5a9dd00df
2011-12-15 00:43:35 -05:00
gloh
aab7397324 config: command line option to specify ruby output file
--HG--
extra : rebase_source : df2237b2ce01b1a3e1d6f112a62deadde4d92420
2011-12-01 10:08:52 -08:00
Chris Emmons
9aea847f58 VNC: Add support for capturing frame buffer to file each time it is changed.
When a change in the frame buffer from the VNC server is detected, the new
frame is stored out to the m5out/frames_*/ directory.  Specifiy the flag
"--frame-capture" when running configs/example/fs.py to enable this behavior.

--HG--
extra : rebase_source : d4e08e83f4fa6ff79f3dc9c433fc1f0487e057fc
2011-12-01 00:15:26 -08:00
Chander Sudanthi
61c14da751 O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
There are two lines in O3CPU.py that set the dcache and icache
tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr.
This patch removes these hardcoded lines from O3CPU.py and sets the default
L1 cache mshr targets to 20.

--HG--
extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b
2011-12-01 00:15:22 -08:00
Tushar Krishna
ac993964a9 GARNET: adding a fault model for resilient on-chip network research.
This patch adds a fault model, which provides the probability of a number of
architectural faults in the interconnection network (e.g., data corruption,
misrouting). These probabilities can be used to realistically inject faults
in GARNET and faithfully evaluate the effectiveness of novel resilient NoC
architectures.
2011-11-04 18:40:22 -04:00
Nilay Vaish
9344480480 Ruby FS: Add the options for kernel and simulation script
These options were missing from the script ruby_fs.py. This patch adds these
options to the script.
2011-10-29 16:54:57 -05:00
Ali Saidi
f2bfef90c4 ARM: Fix small bug in config script that prevents android from booting 2011-10-19 18:08:31 -05:00
Ali Saidi
ba265abbfd ARM: Add some MP regressions and clean up the disk images and kernels a bit 2011-08-19 15:08:09 -05:00
Ali Saidi
2fd2b44b86 ARM: Add VExpress_E support with PCIe to gem5 2011-08-19 15:08:08 -05:00
Ali Saidi
d2a0a2ec22 ARM: Add support for Versatile Express boards 2011-08-19 15:08:08 -05:00
Nilay Vaish
1b49c56679 Scons: Drop RUBY as compile time option.
This patch drops RUBY as a compile time option. Instead the PROTOCOL option
is used to figure out whether or not to build Ruby. If the specified protocol
is 'None', then Ruby is not compiled.
2011-08-02 00:10:08 -05:00
Nilay Vaish
00ad4eb8ce Ruby: Fix instantiations of DMA controller and sequencer
The patch on Ruby functional accesses made changes to the process of
instantiating controllers and sequencers. The DMA controller and
sequencer was not updated, hence this patch.
2011-07-26 12:20:22 -05:00
Nilay Vaish
ca247a81f0 Ruby: Fix dma controller configs/ruby/MI_example.py
The dma controller in configs/ruby/MI_example.py was not being set correctly.
This patch fixes it.
2011-07-25 18:18:31 -05:00
Nilay Vaish
d919930c3c se.py: Fixes the way ruby's options are added 2011-07-11 19:57:10 -05:00
Nilay Vaish
5e0851d554 Network_test: Conform it with functional access changes in Ruby
Addition of functional access support to Ruby necessitated some changes to
the way coherence protocols are written. I had forgotten to update the
Network_test protocol. This patch makes those updates.
2011-07-03 11:33:46 -05:00
Brad Beckmann
0b7b3766af config: removed unnecessary slashes
This patch removes unnecessary slashes from a couple of python scripts.
2011-06-30 19:54:02 -05:00
Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
c86f849d5a Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
2011-06-30 19:49:26 -05:00
Gedare Bloom
3f1f16703d ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA. 2011-06-17 12:20:10 -05:00
Steve Reinhardt
19bb896bfe config: revamp x86 config to avoid appending to SimObjectVectors
A significant contributor to the need for adoptOrphanParams()
is the practice of appending to SimObjectVectors which have
already been assigned as children.  This practice sidesteps the
assignment operation for those appended SimObjects, which is
where parent/child relationships are typically established.

This patch reworks the config scripts that use append() on
SimObjectVectors, which all happen to be in the x86 system
configuration.  At some point in the future, I hope to make
SimObjectVectors immutable (by deriving from tuple rather than
list), at which time this patch will be necessary for correct
operation.  For now, it just avoids some of the warning
messages that get printed in adoptOrphanParams().
2011-05-23 14:29:23 -07:00