Chander Sudanthi 61c14da751 O3: Remove hardcoded tgts_per_mshr in O3CPU.py. ... There are two lines in O3CPU.py that set the dcache and icache tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr. This patch removes these hardcoded lines from O3CPU.py and sets the default L1 cache mshr targets to 20. --HG-- extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b		2011-12-01 00:15:22 -08:00
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boot	ARM: Include IDE/CF controller by default in PBX model.	2011-04-04 11:42:31 -05:00
common	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	2011-12-01 00:15:22 -08:00
example	Ruby FS: Add the options for kernel and simulation script	2011-10-29 16:54:57 -05:00
ruby	GARNET: adding a fault model for resilient on-chip network research.	2011-11-04 18:40:22 -04:00
splash2	Config: Keep track of uncached and cached ports separately.	2011-02-03 20:23:00 -08:00