Chander Sudanthi 61c14da751 O3: Remove hardcoded tgts_per_mshr in O3CPU.py. ... There are two lines in O3CPU.py that set the dcache and icache tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr. This patch removes these hardcoded lines from O3CPU.py and sets the default L1 cache mshr targets to 20. --HG-- extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b		2011-12-01 00:15:22 -08:00
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Benchmarks.py	ARM: Add some MP regressions and clean up the disk images and kernels a bit	2011-08-19 15:08:09 -05:00
CacheConfig.py	configs: cache: add cache line size option	2011-02-23 14:26:55 -05:00
Caches.py	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	2011-12-01 00:15:22 -08:00
cpu2000.py	python: fix another bug from changes to main.py	2011-04-20 19:07:44 -07:00
FSConfig.py	ARM: Fix small bug in config script that prevents android from booting	2011-10-19 18:08:31 -05:00
Options.py	configs: cleanup redundant/unused options	2011-05-20 14:49:06 -04:00
Simulation.py	configs: missed spot progress-interval change	2011-05-23 14:36:22 -04:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00