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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

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ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
---------- Begin Simulation Statistics ----------
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
sim_seconds 2.617033 # Number of seconds simulated
sim_ticks 2617033170500 # Number of ticks simulated
final_tick 2617033170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
host_inst_rate 88113 # Simulator instruction rate (inst/s)
host_op_rate 113402 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3655705591 # Simulator tick rate (ticks/s)
host_mem_usage 391256 # Number of bytes of host memory used
host_seconds 715.88 # Real time elapsed on the host
sim_insts 63077791 # Number of instructions simulated
sim_ops 81181923 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.physmem.bytes_read::cpu0.inst 395840 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4357428 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 425152 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 5244336 # Number of bytes read from this memory
system.physmem.bytes_read::total 131535204 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 395840 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 425152 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 820992 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4255104 # Number of bytes written to this memory
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.physmem.bytes_written::total 7284240 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.physmem.num_reads::cpu0.inst 6185 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 68157 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 6643 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 81969 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15301800 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66486 # Number of write requests responded to by this memory
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.physmem.num_writes::total 823770 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 46277796 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 245 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 151255 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1665026 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 440 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 162456 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 2003924 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50261191 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 151255 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 162456 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 313711 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1625927 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 1150974 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2783396 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1625927 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 46277796 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 245 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 151255 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1671522 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 440 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 162456 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 3154898 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53044587 # Total bandwidth to/from this memory (bytes/s)
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 24 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 171 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 24 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 171 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 72594 # number of replacements
system.l2c.tagsinuse 53100.305923 # Cycle average of tags in use
system.l2c.total_refs 1970249 # Total number of references to valid blocks.
system.l2c.sampled_refs 137794 # Sample count of references to valid blocks.
system.l2c.avg_refs 14.298511 # Average number of references to valid blocks.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.occ_blocks::writebacks 37791.704596 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 4.504480 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.004560 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 4202.741800 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 2939.105076 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 13.484693 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 4025.080355 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 4123.680364 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.576656 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000069 # Average percentage of cache occupancy
ARM: Update stats for IT and conditional branch changes
2012-03-21 16:36:45 +01:00
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.occ_percent::cpu0.inst 0.064129 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.044847 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000206 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.061418 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.062922 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.810246 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 54561 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 5750 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 401038 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 165879 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 78192 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 6577 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 616294 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 201951 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1530242 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 584193 # number of Writeback hits
system.l2c.Writeback_hits::total 584193 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 1046 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 814 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 1860 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 204 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 171 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 375 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 48310 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 58954 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 107264 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 54561 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 5750 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 401038 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 214189 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 78192 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 6577 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 616294 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 260905 # number of demand (read+write) hits
system.l2c.demand_hits::total 1637506 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 54561 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 5750 # number of overall hits
system.l2c.overall_hits::cpu0.inst 401038 # number of overall hits
system.l2c.overall_hits::cpu0.data 214189 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 78192 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 6577 # number of overall hits
system.l2c.overall_hits::cpu1.inst 616294 # number of overall hits
system.l2c.overall_hits::cpu1.data 260905 # number of overall hits
system.l2c.overall_hits::total 1637506 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 10 # number of ReadReq misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.ReadReq_misses::cpu0.inst 6056 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 6316 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 6605 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 6313 # number of ReadReq misses
system.l2c.ReadReq_misses::total 25320 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 5689 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 4311 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 10000 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 783 # number of SCUpgradeReq misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.SCUpgradeReq_misses::cpu1.data 578 # number of SCUpgradeReq misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.SCUpgradeReq_misses::total 1361 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 63204 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 76879 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 140083 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 10 # number of demand (read+write) misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.demand_misses::cpu0.inst 6056 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 69520 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 6605 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 83192 # number of demand (read+write) misses
system.l2c.demand_misses::total 165403 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 10 # number of overall misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.overall_misses::cpu0.inst 6056 # number of overall misses
system.l2c.overall_misses::cpu0.data 69520 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 18 # number of overall misses
system.l2c.overall_misses::cpu1.inst 6605 # number of overall misses
system.l2c.overall_misses::cpu1.data 83192 # number of overall misses
system.l2c.overall_misses::total 165403 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 522500 # number of ReadReq miss cycles
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 112500 # number of ReadReq miss cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.ReadReq_miss_latency::cpu0.inst 322936498 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 331707998 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 952500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 351349999 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 331785500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1339367495 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 20090481 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 27401499 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 47491980 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1617500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6565000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 8182500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 3365710489 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 4075887489 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 7441597978 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 522500 # number of demand (read+write) miss cycles
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.demand_miss_latency::cpu0.itb.walker 112500 # number of demand (read+write) miss cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.demand_miss_latency::cpu0.inst 322936498 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 3697418487 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 952500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 351349999 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 4407672989 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 8780965473 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 522500 # number of overall miss cycles
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.overall_miss_latency::cpu0.itb.walker 112500 # number of overall miss cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.overall_miss_latency::cpu0.inst 322936498 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 3697418487 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 952500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 351349999 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 4407672989 # number of overall miss cycles
system.l2c.overall_miss_latency::total 8780965473 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 54571 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 5752 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 407094 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 172195 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 78210 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 6577 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 622899 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 208264 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1555562 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 584193 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 584193 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 6735 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 5125 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 11860 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 987 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 749 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1736 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 111514 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 135833 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 247347 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 54571 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 5752 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 407094 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 283709 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 78210 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 6577 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 622899 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 344097 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1802909 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 54571 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 5752 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 407094 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 283709 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 78210 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 6577 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 622899 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 344097 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1802909 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000183 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000348 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014876 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.036679 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000230 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.010604 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.030312 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.016277 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.844692 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.841171 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.843170 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.793313 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.771696 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.783986 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.566781 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.565982 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.566342 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000183 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000348 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014876 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.245040 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000230 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.010604 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.241769 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.091742 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000183 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000348 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.014876 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.245040 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000230 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.010604 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.241769 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.091742 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52250 # average ReadReq miss latency
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 56250 # average ReadReq miss latency
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53325.049207 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52518.682394 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52916.666667 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53194.549432 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52555.916363 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52897.610387 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3531.460889 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6356.181628 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 4749.198000 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2065.772669 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11358.131488 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 6012.123439 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53251.542450 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53016.916050 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 53122.777054 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52250 # average overall miss latency
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 56250 # average overall miss latency
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.demand_avg_miss_latency::cpu0.inst 53325.049207 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 53184.960975 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52916.666667 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 53194.549432 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 52981.933227 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 53088.308392 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52250 # average overall miss latency
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 56250 # average overall miss latency
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.overall_avg_miss_latency::cpu0.inst 53325.049207 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 53184.960975 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52916.666667 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 53194.549432 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 52981.933227 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 53088.308392 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.writebacks::writebacks 66486 # number of writebacks
system.l2c.writebacks::total 66486 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data 40 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 25 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 40 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 25 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 40 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 25 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 76 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 10 # number of ReadReq MSHR misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 6052 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 6276 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 18 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 6598 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 6288 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 25244 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 5689 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 4311 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 10000 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 783 # number of SCUpgradeReq MSHR misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 578 # number of SCUpgradeReq MSHR misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.SCUpgradeReq_mshr_misses::total 1361 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 63204 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 76879 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 140083 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 10 # number of demand (read+write) MSHR misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.demand_mshr_misses::cpu0.inst 6052 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 69480 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 18 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 6598 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 83167 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 165327 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 10 # number of overall MSHR misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.overall_mshr_misses::cpu0.inst 6052 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 69480 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 18 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 6598 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 83167 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 165327 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 400000 # number of ReadReq MSHR miss cycles
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 88000 # number of ReadReq MSHR miss cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 248870498 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 253621500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 733500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270526499 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 254062500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1028302497 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 227738000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 172587000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 400325000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31335500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23126500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 54462000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2597363499 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3131334993 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 5728698492 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 400000 # number of demand (read+write) MSHR miss cycles
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 88000 # number of demand (read+write) MSHR miss cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.demand_mshr_miss_latency::cpu0.inst 248870498 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 2850984999 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 733500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 270526499 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 3385397493 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 6757000989 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 400000 # number of overall MSHR miss cycles
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 88000 # number of overall MSHR miss cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.overall_mshr_miss_latency::cpu0.inst 248870498 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 2850984999 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 733500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 270526499 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 3385397493 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 6757000989 # number of overall MSHR miss cycles
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5579000 # number of ReadReq MSHR uncacheable cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12326324000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2170500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154700128500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167034202000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1153610999 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31143367304 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 32296978303 # number of WriteReq MSHR uncacheable cycles
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5579000 # number of overall MSHR uncacheable cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13479934999 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2170500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185843495804 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 199331180303 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000183 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000348 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036447 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000230 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010592 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030192 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.016228 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.844692 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.841171 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.843170 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.793313 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.771696 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.783986 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566781 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565982 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.566342 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000183 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000348 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.244899 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000230 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010592 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.241696 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.091700 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000183 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000348 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014866 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.244899 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000230 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010592 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.241696 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.091700 # mshr miss rate for overall accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average ReadReq mshr miss latency
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40411.328872 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40404.341603 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40734.530859 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.288451 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40034.098817 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.500000 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40019.795658 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40011.245675 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40016.164585 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41094.922774 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40730.693596 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40895.030032 # average ReadExReq mshr miss latency
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41033.175000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40706.019130 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40870.523199 # average overall mshr miss latency
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41122.025446 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41033.175000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41001.288118 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40706.019130 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40870.523199 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.dtb.read_hits 9087709 # DTB read hits
system.cpu0.dtb.read_misses 37707 # DTB read misses
system.cpu0.dtb.write_hits 5292852 # DTB write hits
system.cpu0.dtb.write_misses 6797 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.dtb.flush_entries 2252 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1465 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 402 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 9125416 # DTB read accesses
system.cpu0.dtb.write_accesses 5299649 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.dtb.hits 14380561 # DTB hits
system.cpu0.dtb.misses 44504 # DTB misses
system.cpu0.dtb.accesses 14425065 # DTB accesses
system.cpu0.itb.inst_hits 4426363 # ITB inst hits
system.cpu0.itb.inst_misses 5791 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu0.itb.flush_entries 1409 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.itb.perms_faults 1661 # Number of TLB faults due to permissions restrictions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.itb.inst_accesses 4432154 # ITB inst accesses
system.cpu0.itb.hits 4426363 # DTB hits
system.cpu0.itb.misses 5791 # DTB misses
system.cpu0.itb.accesses 4432154 # DTB accesses
system.cpu0.numCycles 73540541 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.BPredUnit.lookups 6354280 # Number of BP lookups
system.cpu0.BPredUnit.condPredicted 4863798 # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect 316535 # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups 4079773 # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits 3047693 # Number of BTB hits
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.BPredUnit.usedRAS 700511 # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect 30883 # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles 12981968 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 33339853 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 6354280 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 3748204 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 7827899 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 1608255 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 88516 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles 23525864 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 5853 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 77679 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 91798 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 4424514 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 175463 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 2818 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 45755598 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.940589 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.320885 # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.fetch.rateDist::0 37936221 82.91% 82.91% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 625086 1.37% 84.28% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 819758 1.79% 86.07% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 695394 1.52% 87.59% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 800497 1.75% 89.34% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 578636 1.26% 90.60% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 719119 1.57% 92.17% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 370554 0.81% 92.98% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 3210333 7.02% 100.00% # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.fetch.rateDist::total 45755598 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.086405 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.453353 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 13479181 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 23559009 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 7020718 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 606128 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1090562 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 996028 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 66487 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 41577642 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 218603 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1090562 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 14092626 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 6784553 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 14469405 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 6963849 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 2354603 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 40318960 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 2633 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 472928 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 1334672 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents 351 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 40667832 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 182121697 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 182086780 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 34917 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 31702592 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 8965239 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 463825 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 419023 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 5696158 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 7936117 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 5894118 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1139492 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 1233570 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 38069002 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 950684 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 38295497 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 94171 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 6802670 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 14391567 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 261548 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 45755598 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.836958 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.462966 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.iq.issued_per_cycle::0 29855724 65.25% 65.25% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 6336412 13.85% 79.10% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 3245721 7.09% 86.19% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 2523061 5.51% 91.71% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 2111675 4.62% 96.32% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 936021 2.05% 98.37% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 511535 1.12% 99.49% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 181147 0.40% 99.88% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 54302 0.12% 100.00% # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.iq.issued_per_cycle::total 45755598 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.iq.fu_full::IntAlu 27761 2.59% 2.59% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 464 0.04% 2.63% # attempts to use FU when none available
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.iq.fu_full::MemRead 835942 77.99% 80.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 207752 19.38% 100.00% # attempts to use FU when none available
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.iq.FU_type_0::IntAlu 23003680 60.07% 60.21% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 50163 0.13% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 9567598 24.98% 85.32% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 5620993 14.68% 100.00% # Type of FU issued
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.iq.FU_type_0::total 38295497 # Type of FU issued
system.cpu0.iq.rate 0.520740 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 1071919 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.027991 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 123548516 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 45830842 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 35351164 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 8368 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 4748 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 39310727 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 4345 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 327037 # Number of loads that had data forwarded from stores
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.iew.lsq.thread0.squashedLoads 1508258 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3980 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 13847 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 614652 # Number of stores squashed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 2149655 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 5288 # Number of times an access to memory failed due to the cache being blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.iew.iewSquashCycles 1090562 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 4675196 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 127491 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 39158193 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 88903 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 7936117 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 5894118 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 617815 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 49276 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 17780 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 13847 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 160769 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 144529 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 305298 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 37872918 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 9405503 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 422579 # Number of squashed instructions skipped in execute
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.iew.exec_nop 138507 # number of nop insts executed
system.cpu0.iew.exec_refs 14971538 # number of memory reference insts executed
system.cpu0.iew.exec_branches 5077620 # Number of branches executed
system.cpu0.iew.exec_stores 5566035 # Number of stores executed
system.cpu0.iew.exec_rate 0.514994 # Inst execution rate
system.cpu0.iew.wb_sent 37653849 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 35355057 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 18700837 # num instructions producing a value
system.cpu0.iew.wb_consumers 35658328 # num instructions consuming a value
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.iew.wb_rate 0.480756 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.524445 # average fanout of values written-back
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.commit.commitCommittedInsts 24280608 # The number of committed instructions
system.cpu0.commit.commitCommittedOps 32020757 # The number of committed instructions
system.cpu0.commit.commitSquashedInsts 6703968 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 689136 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 267907 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 44701440 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.716325 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.672707 # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.commit.committed_per_cycle::0 32554343 72.83% 72.83% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 6077315 13.60% 86.42% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 1947893 4.36% 90.78% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 1038743 2.32% 93.10% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 803562 1.80% 94.90% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 505193 1.13% 96.03% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 401469 0.90% 96.93% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 200976 0.45% 97.38% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1171946 2.62% 100.00% # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.commit.committed_per_cycle::total 44701440 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 24280608 # Number of instructions committed
system.cpu0.commit.committedOps 32020757 # Number of ops (including micro ops) committed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.commit.refs 11707325 # Number of memory references committed
system.cpu0.commit.loads 6427859 # Number of loads committed
system.cpu0.commit.membars 234599 # Number of memory barriers committed
system.cpu0.commit.branches 4418672 # Number of branches committed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.commit.int_insts 28286546 # Number of committed integer instructions.
system.cpu0.commit.function_calls 500309 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 1171946 # number cycles where commit BW limit reached
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.rob.rob_reads 81369547 # The number of ROB reads
system.cpu0.rob.rob_writes 78542452 # The number of ROB writes
system.cpu0.timesIdled 427204 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 27784943 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 5160481977 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 24199866 # Number of Instructions Simulated
system.cpu0.committedOps 31940015 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 24199866 # Number of Instructions Simulated
system.cpu0.cpi 3.038882 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 3.038882 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.329068 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.329068 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 176731885 # number of integer regfile reads
system.cpu0.int_regfile_writes 35129220 # number of integer regfile writes
system.cpu0.fp_regfile_reads 3381 # number of floating regfile reads
system.cpu0.fp_regfile_writes 940 # number of floating regfile writes
system.cpu0.misc_regfile_reads 47656068 # number of misc regfile reads
system.cpu0.misc_regfile_writes 527809 # number of misc regfile writes
system.cpu0.icache.replacements 407270 # number of replacements
system.cpu0.icache.tagsinuse 511.577657 # Cycle average of tags in use
system.cpu0.icache.total_refs 3982592 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 407782 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 9.766473 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 7275068000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 511.577657 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.999175 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.999175 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 3982592 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 3982592 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 3982592 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 3982592 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 3982592 # number of overall hits
system.cpu0.icache.overall_hits::total 3982592 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 441782 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 441782 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 441782 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 441782 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 441782 # number of overall misses
system.cpu0.icache.overall_misses::total 441782 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7132710997 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 7132710997 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 7132710997 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 7132710997 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 7132710997 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 7132710997 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 4424374 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 4424374 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 4424374 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 4424374 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 4424374 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 4424374 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099852 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.099852 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099852 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.099852 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099852 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.099852 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16145.318272 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 16145.318272 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16145.318272 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 16145.318272 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16145.318272 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 16145.318272 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 1383498 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.icache.blocked::no_mshrs 169 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 8186.378698 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33988 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 33988 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 33988 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 33988 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 33988 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 33988 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407794 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 407794 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 407794 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 407794 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 407794 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 407794 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5471235499 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 5471235499 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5471235499 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 5471235499 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5471235499 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 5471235499 # number of overall MSHR miss cycles
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8379000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8379000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8379000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 8379000 # number of overall MSHR uncacheable cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092170 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.092170 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092170 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.092170 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13416.665029 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13416.665029 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13416.665029 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13416.665029 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13416.665029 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13416.665029 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.dcache.replacements 275687 # number of replacements
system.cpu0.dcache.tagsinuse 476.019935 # Cycle average of tags in use
system.cpu0.dcache.total_refs 9558592 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 276199 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 34.607627 # Average number of references to valid blocks.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.dcache.warmup_cycle 51448000 # Cycle when the warmup percentage was hit.
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.dcache.occ_blocks::cpu0.data 476.019935 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.929726 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.929726 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 5937166 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 5937166 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3229422 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 3229422 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174299 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 174299 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171559 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 171559 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 9166588 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 9166588 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 9166588 # number of overall hits
system.cpu0.dcache.overall_hits::total 9166588 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 401556 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 401556 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1594295 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1594295 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9014 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 9014 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7780 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 7780 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1995851 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1995851 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1995851 # number of overall misses
system.cpu0.dcache.overall_misses::total 1995851 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7292954000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 7292954000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71657694355 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 71657694355 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 113831500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 113831500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90370500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 90370500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 78950648355 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 78950648355 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 78950648355 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 78950648355 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6338722 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 6338722 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4823717 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4823717 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183313 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 183313 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179339 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 179339 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 11162439 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 11162439 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 11162439 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 11162439 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063350 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.063350 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330512 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.330512 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049173 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.049173 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043382 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043382 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178801 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.178801 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178801 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.178801 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18161.735848 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 18161.735848 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44946.320697 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 44946.320697 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12628.300422 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12628.300422 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11615.745501 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11615.745501 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39557.385975 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 39557.385975 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39557.385975 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 39557.385975 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 7317992 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 1712000 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 1467 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 85 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4988.406271 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 20141.176471 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.dcache.writebacks::writebacks 255942 # number of writebacks
system.cpu0.dcache.writebacks::total 255942 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 212150 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 212150 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463164 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1463164 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 530 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 530 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1675314 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1675314 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1675314 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1675314 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189406 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 189406 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131131 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 131131 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8484 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8484 # number of LoadLockedReq MSHR misses
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7773 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7773 # number of StoreCondReq MSHR misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.dcache.demand_mshr_misses::cpu0.data 320537 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 320537 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 320537 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 320537 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2811014487 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2811014487 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4674099005 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4674099005 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79244002 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79244002 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 65918035 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 65918035 # number of StoreCondReq MSHR miss cycles
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7485113492 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 7485113492 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7485113492 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 7485113492 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13455989500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13455989500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1298746899 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1298746899 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14754736399 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14754736399 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029881 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029881 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027185 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027185 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046281 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046281 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043342 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043342 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028716 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.028716 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028716 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.028716 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14841.211403 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14841.211403 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35644.500576 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35644.500576 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9340.405705 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9340.405705 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8480.385308 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8480.385308 # average StoreCondReq mshr miss latency
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23351.792436 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23351.792436 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23351.792436 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23351.792436 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.dtb.read_hits 43452334 # DTB read hits
system.cpu1.dtb.read_misses 46277 # DTB read misses
system.cpu1.dtb.write_hits 7091337 # DTB write hits
system.cpu1.dtb.write_misses 12150 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.dtb.flush_entries 2524 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 3762 # Number of TLB faults due to alignment restrictions
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu1.dtb.prefetch_faults 371 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.dtb.perms_faults 692 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 43498611 # DTB read accesses
system.cpu1.dtb.write_accesses 7103487 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.dtb.hits 50543671 # DTB hits
system.cpu1.dtb.misses 58427 # DTB misses
system.cpu1.dtb.accesses 50602098 # DTB accesses
system.cpu1.itb.inst_hits 9232744 # ITB inst hits
system.cpu1.itb.inst_misses 6115 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.itb.flush_entries 1606 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.itb.perms_faults 1727 # Number of TLB faults due to permissions restrictions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.itb.inst_accesses 9238859 # ITB inst accesses
system.cpu1.itb.hits 9232744 # DTB hits
system.cpu1.itb.misses 6115 # DTB misses
system.cpu1.itb.accesses 9238859 # DTB accesses
system.cpu1.numCycles 420389270 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.BPredUnit.lookups 9847995 # Number of BP lookups
system.cpu1.BPredUnit.condPredicted 8081754 # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect 448433 # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups 6818773 # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits 5657403 # Number of BTB hits
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.BPredUnit.usedRAS 833939 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 50420 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 22177481 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 71987538 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 9847995 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 6491342 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 15338669 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 4640041 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 86616 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles 81067805 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 5869 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 63713 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 142087 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 99 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 9230611 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 860735 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 3603 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 122048207 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.712843 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.062128 # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.fetch.rateDist::0 106717875 87.44% 87.44% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 829211 0.68% 88.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 1015415 0.83% 88.95% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 2063306 1.69% 90.64% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 1641471 1.34% 91.99% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 615009 0.50% 92.49% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 2274741 1.86% 94.35% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 467540 0.38% 94.74% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 6423639 5.26% 100.00% # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.fetch.rateDist::total 122048207 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.023426 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.171240 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 23807304 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 80829213 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 13786228 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 560401 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 3065061 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 1241341 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 102643 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 81234919 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 343119 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 3065061 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 25364340 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 34010393 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 42304537 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 12707018 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 4596858 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 74746383 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 20429 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 720817 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 3279864 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents 33412 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 79106997 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 344419030 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 344359691 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 59339 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 50193146 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 28913851 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 487769 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 421850 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 8399849 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 14034972 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 8614706 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 1072487 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 1529720 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 67446295 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 1206628 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 91979521 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 109681 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 18910261 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 53596675 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 286825 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 122048207 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.753633 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.492572 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.iq.issued_per_cycle::0 90230410 73.93% 73.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 9124502 7.48% 81.41% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 4577298 3.75% 85.16% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 4017634 3.29% 88.45% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 10703333 8.77% 97.22% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1977632 1.62% 98.84% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 1055737 0.87% 99.70% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 281681 0.23% 99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 79980 0.07% 100.00% # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.iq.issued_per_cycle::total 122048207 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.iq.fu_full::IntAlu 28913 0.37% 0.37% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 998 0.01% 0.38% # attempts to use FU when none available
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.iq.fu_full::MemRead 7574685 95.84% 96.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 298874 3.78% 100.00% # attempts to use FU when none available
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.iq.FU_type_0::IntAlu 39479578 42.92% 43.26% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 61492 0.07% 43.33% # Type of FU issued
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.33% # Type of FU issued
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 43.33% # Type of FU issued
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.33% # Type of FU issued
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.iq.FU_type_0::SimdShift 6 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.33% # Type of FU issued
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.33% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.33% # Type of FU issued
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.iq.FU_type_0::SimdFloatMisc 1697 0.00% 43.33% # Type of FU issued
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.33% # Type of FU issued
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.33% # Type of FU issued
stats: update stats for icache change not allowing dirty data
2012-07-27 22:08:05 +02:00
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.33% # Type of FU issued
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.iq.FU_type_0::MemRead 44651207 48.54% 91.88% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 7471778 8.12% 100.00% # Type of FU issued
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.iq.FU_type_0::total 91979521 # Type of FU issued
system.cpu1.iq.rate 0.218796 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 7903470 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.085926 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 314063875 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 87576510 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 55784562 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 14814 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 8109 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 99561488 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 7766 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 369403 # Number of loads that had data forwarded from stores
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.iew.lsq.thread0.squashedLoads 4042367 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 6847 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 22042 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 1594624 # Number of stores squashed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 31965742 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 1047944 # Number of times an access to memory failed due to the cache being blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.iew.iewSquashCycles 3065061 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 25634357 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 409319 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 68777683 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 134755 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 14034972 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 8614706 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 896270 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 80399 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 14951 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 22042 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 226446 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 198201 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 424647 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 89117462 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 43838045 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 2862059 # Number of squashed instructions skipped in execute
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.iew.exec_nop 124760 # number of nop insts executed
system.cpu1.iew.exec_refs 51234744 # number of memory reference insts executed
system.cpu1.iew.exec_branches 7395685 # Number of branches executed
system.cpu1.iew.exec_stores 7396699 # Number of stores executed
system.cpu1.iew.exec_rate 0.211988 # Inst execution rate
system.cpu1.iew.wb_sent 87946957 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 55791363 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 30796912 # num instructions producing a value
system.cpu1.iew.wb_consumers 54575062 # num instructions consuming a value
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.iew.wb_rate 0.132714 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.564304 # average fanout of values written-back
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.commit.commitCommittedInsts 38947564 # The number of committed instructions
system.cpu1.commit.commitCommittedOps 49311547 # The number of committed instructions
system.cpu1.commit.commitSquashedInsts 19037243 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 919803 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 377326 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 119031582 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.414273 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.369590 # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.commit.committed_per_cycle::0 101746657 85.48% 85.48% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 8535054 7.17% 92.65% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 2209116 1.86% 94.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 1312161 1.10% 95.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1288209 1.08% 96.69% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 590684 0.50% 97.19% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 998098 0.84% 98.02% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 485890 0.41% 98.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1865713 1.57% 100.00% # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.commit.committed_per_cycle::total 119031582 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 38947564 # Number of instructions committed
system.cpu1.commit.committedOps 49311547 # Number of ops (including micro ops) committed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.commit.refs 17012687 # Number of memory references committed
system.cpu1.commit.loads 9992605 # Number of loads committed
system.cpu1.commit.membars 202357 # Number of memory barriers committed
system.cpu1.commit.branches 6222202 # Number of branches committed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.commit.int_insts 43701968 # Number of committed integer instructions.
system.cpu1.commit.function_calls 556417 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 1865713 # number cycles where commit BW limit reached
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.rob.rob_reads 184400014 # The number of ROB reads
system.cpu1.rob.rob_writes 139856425 # The number of ROB writes
system.cpu1.timesIdled 1519588 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 298341063 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 4812976632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 38877925 # Number of Instructions Simulated
system.cpu1.committedOps 49241908 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 38877925 # Number of Instructions Simulated
system.cpu1.cpi 10.813058 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 10.813058 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.092481 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.092481 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 398800057 # number of integer regfile reads
system.cpu1.int_regfile_writes 58498146 # number of integer regfile writes
system.cpu1.fp_regfile_reads 4943 # number of floating regfile reads
system.cpu1.fp_regfile_writes 2344 # number of floating regfile writes
system.cpu1.misc_regfile_reads 91875872 # number of misc regfile reads
system.cpu1.misc_regfile_writes 429758 # number of misc regfile writes
system.cpu1.icache.replacements 623101 # number of replacements
system.cpu1.icache.tagsinuse 498.730815 # Cycle average of tags in use
system.cpu1.icache.total_refs 8556871 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 623613 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 13.721444 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 75785780000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 498.730815 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.974084 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.974084 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 8556871 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 8556871 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 8556871 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 8556871 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 8556871 # number of overall hits
system.cpu1.icache.overall_hits::total 8556871 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 673686 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 673686 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 673686 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 673686 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 673686 # number of overall misses
system.cpu1.icache.overall_misses::total 673686 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10642693998 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 10642693998 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 10642693998 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 10642693998 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 10642693998 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 10642693998 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 9230557 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 9230557 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 9230557 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 9230557 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 9230557 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 9230557 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.072984 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.072984 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.072984 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.072984 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.072984 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.072984 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15797.706941 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 15797.706941 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15797.706941 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 15797.706941 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15797.706941 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 15797.706941 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 1133998 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.icache.blocked::no_mshrs 174 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs 6517.229885 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50044 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 50044 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 50044 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 50044 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 50044 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 50044 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 623642 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 623642 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 623642 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 623642 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 623642 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 623642 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8149352498 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 8149352498 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8149352498 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 8149352498 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8149352498 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 8149352498 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3211500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3211500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3211500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 3211500 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067563 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.067563 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067563 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.067563 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13067.356750 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13067.356750 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13067.356750 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13067.356750 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.dcache.replacements 363581 # number of replacements
system.cpu1.dcache.tagsinuse 487.223522 # Cycle average of tags in use
system.cpu1.dcache.total_refs 13117187 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 363929 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 36.043258 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 71474573000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 487.223522 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.951608 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.951608 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 8616147 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 8616147 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 4254446 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 4254446 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105790 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 105790 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100736 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 100736 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 12870593 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 12870593 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 12870593 # number of overall hits
system.cpu1.dcache.overall_hits::total 12870593 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 410065 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 410065 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 1595508 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 1595508 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14278 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 14278 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10912 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 10912 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 2005573 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 2005573 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 2005573 # number of overall misses
system.cpu1.dcache.overall_misses::total 2005573 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8126055000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 8126055000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66044305227 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 66044305227 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166791500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 166791500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 95304000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 95304000 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 74170360227 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 74170360227 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 74170360227 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 74170360227 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 9026212 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 9026212 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 5849954 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 5849954 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 120068 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 120068 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111648 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 111648 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 14876166 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 14876166 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 14876166 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 14876166 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045430 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.045430 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272739 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.272739 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118916 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118916 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097736 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097736 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134818 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.134818 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134818 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.134818 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19816.504700 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 19816.504700 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41393.904153 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 41393.904153 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11681.713125 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11681.713125 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8733.870968 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8733.870968 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 36982.129410 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 36982.129410 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 36982.129410 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 36982.129410 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 29670016 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 5568500 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 6658 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 173 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4456.295584 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 32187.861272 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.dcache.writebacks::writebacks 328251 # number of writebacks
system.cpu1.dcache.writebacks::total 328251 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178277 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 178277 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432587 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 1432587 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1464 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1464 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1610864 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 1610864 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1610864 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 1610864 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231788 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 231788 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162921 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 162921 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12814 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12814 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10909 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 10909 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 394709 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 394709 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 394709 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 394709 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3566201462 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3566201462 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5537603585 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5537603585 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104573506 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104573506 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61265506 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61265506 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9103805047 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 9103805047 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9103805047 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 9103805047 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169309741500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169309741500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40933880282 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40933880282 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210243621782 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210243621782 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025679 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025679 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027850 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027850 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106723 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106723 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097709 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097709 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026533 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.026533 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026533 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.026533 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15385.617297 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15385.617297 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33989.501568 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33989.501568 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8160.879195 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8160.879195 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5616.051517 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5616.051517 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23064.599609 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23064.599609 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23064.599609 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23064.599609 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_refs nan # Average number of references to valid blocks.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323189312111 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1323189312111 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323189312111 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1323189312111 # number of overall MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu0.kern.inst.quiesce 43824 # number of quiesce instructions executed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
Device: Update stats for PIO and PCI latency change This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10 17:57:37 +02:00
system.cpu1.kern.inst.quiesce 53932 # number of quiesce instructions executed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink