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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

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ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
---------- Begin Simulation Statistics ----------
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
sim_seconds 2.581528 # Number of seconds simulated
sim_ticks 2581527583500 # Number of ticks simulated
final_tick 2581527583500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
host_inst_rate 89313 # Simulator instruction rate (inst/s)
host_op_rate 115365 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 3717496726 # Simulator tick rate (ticks/s)
host_mem_usage 390980 # Number of bytes of host memory used
host_seconds 694.43 # Real time elapsed on the host
sim_insts 62021206 # Number of instructions simulated
sim_ops 80112751 # Number of ops (including micro ops) simulated
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 320 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.realview.nvmem.bw_read::cpu1.inst 124 # Total read bandwidth from this memory (bytes/s)
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.realview.nvmem.bw_inst_read::cpu1.inst 124 # Instruction read bandwidth from this memory (bytes/s)
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s)
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 395008 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4372084 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 425536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 5226480 # Number of bytes read from this memory
system.physmem.bytes_read::total 129958756 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 395008 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 425536 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 820544 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4244480 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
system.physmem.bytes_written::total 7273616 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 6172 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 68386 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 6649 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 81690 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15105136 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66320 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
system.physmem.num_writes::total 823604 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 46305011 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 223 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 153013 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1693603 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 521 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 164839 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 2024569 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50341804 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 153013 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 164839 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 317852 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1644174 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6585 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 1166804 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2817563 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1644174 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 46305011 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 223 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 153013 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1700189 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 521 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 164839 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 3191372 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53159367 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 72536 # number of replacements
system.l2c.tagsinuse 53024.626088 # Cycle average of tags in use
system.l2c.total_refs 2019266 # Total number of references to valid blocks.
system.l2c.sampled_refs 137732 # Sample count of references to valid blocks.
system.l2c.avg_refs 14.660834 # Average number of references to valid blocks.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.occ_blocks::writebacks 37701.415204 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 3.259804 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.000179 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 4215.968317 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.data 2959.624437 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 13.637835 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 4028.150256 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 4102.570055 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.575278 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000050 # Average percentage of cache occupancy
ARM: Update stats for IT and conditional branch changes
2012-03-21 16:36:45 +01:00
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.occ_percent::cpu0.inst 0.064331 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.045160 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000208 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.061465 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.062600 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.809092 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 53338 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 6106 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 398719 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 164464 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 78886 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 6452 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 615129 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 199702 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1522796 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 645710 # number of Writeback hits
system.l2c.Writeback_hits::total 645710 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 1043 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 806 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 1849 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 213 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 356 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 48030 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 59189 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 107219 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 53338 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 6106 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 398719 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 212494 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 78886 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 6452 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 615129 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 258891 # number of demand (read+write) hits
system.l2c.demand_hits::total 1630015 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 53338 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 6106 # number of overall hits
system.l2c.overall_hits::cpu0.inst 398719 # number of overall hits
system.l2c.overall_hits::cpu0.data 212494 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 78886 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 6452 # number of overall hits
system.l2c.overall_hits::cpu1.inst 615129 # number of overall hits
system.l2c.overall_hits::cpu1.data 258891 # number of overall hits
system.l2c.overall_hits::total 1630015 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 9 # number of ReadReq misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_misses::cpu0.inst 6044 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 6302 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 21 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 6609 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 6328 # number of ReadReq misses
system.l2c.ReadReq_misses::total 25314 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 5683 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 4287 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 9970 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 777 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 589 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1366 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 63451 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 76572 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 140023 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_misses::cpu0.inst 6044 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 69753 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 21 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 6609 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 82900 # number of demand (read+write) misses
system.l2c.demand_misses::total 165337 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 9 # number of overall misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_misses::cpu0.inst 6044 # number of overall misses
system.l2c.overall_misses::cpu0.data 69753 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 21 # number of overall misses
system.l2c.overall_misses::cpu1.inst 6609 # number of overall misses
system.l2c.overall_misses::cpu1.data 82900 # number of overall misses
system.l2c.overall_misses::total 165337 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 471000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 60000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 322261499 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 330895497 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1101000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 351559997 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 332583499 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1338932492 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 20202500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 27410499 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 47612999 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1721500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7138500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 8860000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 3379920986 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 4071556980 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 7451477966 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 471000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 60000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 322261499 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 3710816483 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 1101000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 351559997 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 4404140479 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 8790410458 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 471000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 60000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 322261499 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 3710816483 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 1101000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 351559997 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 4404140479 # number of overall miss cycles
system.l2c.overall_miss_latency::total 8790410458 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 53347 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 6107 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 404763 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 170766 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 78907 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 6452 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 621738 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 206030 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1548110 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 645710 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 645710 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 6726 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 5093 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 11819 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 990 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 732 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1722 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 111481 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 135761 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 247242 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 53347 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 6107 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 404763 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 282247 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 78907 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 6452 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 621738 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 341791 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1795352 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 53347 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 6107 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 404763 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 282247 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 78907 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 6452 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 621738 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 341791 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1795352 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000169 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000164 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014932 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.036904 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000266 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.010630 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.030714 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.016352 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.844930 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.841744 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.843557 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784848 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.804645 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.793264 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.569164 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.564021 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.566340 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000169 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000164 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014932 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.247135 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000266 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.010630 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.242546 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.092092 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000169 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000164 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.014932 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.247135 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000266 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.010630 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.242546 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.092092 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52333.333333 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 60000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53319.242058 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 52506.426055 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52428.571429 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53194.128764 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 52557.442952 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 52892.964052 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3554.900581 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6393.864941 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 4775.626780 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2215.572716 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12119.694397 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 6486.090776 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53268.206742 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53172.921956 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 53216.099969 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52333.333333 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 60000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 53319.242058 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 53199.381862 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52428.571429 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 53194.128764 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 53125.940639 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 53166.626091 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52333.333333 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 60000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 53319.242058 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 53199.381862 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52428.571429 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 53194.128764 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 53125.940639 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 53166.626091 # average overall miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.writebacks::writebacks 66320 # number of writebacks
system.l2c.writebacks::total 66320 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 23 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0.data 1 # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 40 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 40 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_mshr_hits::total 73 # number of overall MSHR hits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 9 # number of ReadReq MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 6039 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 6263 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 21 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 6604 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 6305 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 25242 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 5683 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 4287 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 9970 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 777 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 589 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1366 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 63450 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 76572 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 140022 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 9 # number of demand (read+write) MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_mshr_misses::cpu0.inst 6039 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 69713 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 21 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 6604 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 82877 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 165264 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 9 # number of overall MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_mshr_misses::cpu0.inst 6039 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 69713 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 21 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 6604 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 82877 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 165264 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 360000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 48000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 248302999 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 253032000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 846000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270719997 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 254713500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1028022496 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 227576000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 171718000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 399294000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31112500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23586500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 54699000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2608560498 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3134816489 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 5743376987 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 360000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 48000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 248302999 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 2861592498 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 846000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 270719997 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 3389529989 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 6771399483 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 360000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 48000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 248302999 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 2861592498 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 846000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 270719997 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 3389529989 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 6771399483 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5579000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9186859000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2133500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122397706500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 131592278000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 704572999 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30781654107 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 31486227106 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5579000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9891431999 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2133500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 153179360607 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 163078505106 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036676 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030602 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.016305 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.844930 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.841744 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.843557 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784848 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.804645 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.793264 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569155 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564021 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.566336 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.242479 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.092051 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.242479 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.092051 # mshr miss rate for overall accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40401.085742 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40398.651864 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 40726.665716 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40045.046630 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40055.516678 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40049.548646 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.827542 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40044.991511 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40043.191801 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41112.064586 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40939.462062 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 41017.675701 # average ReadExReq mshr miss latency
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41048.190409 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40898.319063 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 40973.227581 # average overall mshr miss latency
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41048.190409 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40898.319063 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 40973.227581 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.dtb.read_hits 9084255 # DTB read hits
system.cpu0.dtb.read_misses 36769 # DTB read misses
system.cpu0.dtb.write_hits 5284576 # DTB write hits
system.cpu0.dtb.write_misses 6773 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.dtb.flush_entries 2261 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 1412 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 383 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.dtb.perms_faults 588 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 9121024 # DTB read accesses
system.cpu0.dtb.write_accesses 5291349 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.dtb.hits 14368831 # DTB hits
system.cpu0.dtb.misses 43542 # DTB misses
system.cpu0.dtb.accesses 14412373 # DTB accesses
system.cpu0.itb.inst_hits 4421795 # ITB inst hits
system.cpu0.itb.inst_misses 5958 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.itb.flush_entries 1415 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.itb.perms_faults 1713 # Number of TLB faults due to permissions restrictions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.itb.inst_accesses 4427753 # ITB inst accesses
system.cpu0.itb.hits 4421795 # DTB hits
system.cpu0.itb.misses 5958 # DTB misses
system.cpu0.itb.accesses 4427753 # DTB accesses
system.cpu0.numCycles 66112093 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.BPredUnit.lookups 6172143 # Number of BP lookups
system.cpu0.BPredUnit.condPredicted 4680207 # Number of conditional branches predicted
system.cpu0.BPredUnit.condIncorrect 316413 # Number of conditional branches incorrect
system.cpu0.BPredUnit.BTBLookups 3902841 # Number of BTB lookups
system.cpu0.BPredUnit.BTBHits 2861272 # Number of BTB hits
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.BPredUnit.usedRAS 700420 # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect 30889 # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles 12972431 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 32579396 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 6172143 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 3561692 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 7636967 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 1568394 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 92289 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.BlockedCycles 21876805 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 5742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 73340 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 91549 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 175 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 4419869 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 175391 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 2999 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 43870869 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.963501 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.353712 # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.fetch.rateDist::0 36242473 82.61% 82.61% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 623814 1.42% 84.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 820212 1.87% 85.90% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 686089 1.56% 87.47% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 622737 1.42% 88.89% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 578948 1.32% 90.21% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 720296 1.64% 91.85% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 370745 0.85% 92.69% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 3205555 7.31% 100.00% # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.fetch.rateDist::total 43870869 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.093359 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.492790 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 13461534 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 21912526 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 6836712 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 603785 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1056312 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 995110 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 66550 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 40827533 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 217718 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1056312 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 14066817 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 6153021 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 13456769 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 6788701 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 2349249 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 39593607 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 1040 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 472233 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LSQFullEvents 1335984 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.FullRegisterEvents 103 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 39791095 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 179675714 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 179640853 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 34861 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 31537071 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 8254023 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 463697 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 419128 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 5673165 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 7928571 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 5881726 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1132931 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 1238845 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 37538443 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 794373 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 37739879 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 92690 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 6264606 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 14354053 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 137507 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 43870869 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.860249 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.478315 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.iq.issued_per_cycle::0 28164784 64.20% 64.20% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 6326126 14.42% 78.62% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 3234526 7.37% 85.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 2361316 5.38% 91.37% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 2098246 4.78% 96.16% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 936106 2.13% 98.29% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 514694 1.17% 99.46% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 181493 0.41% 99.88% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 53578 0.12% 100.00% # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.iq.issued_per_cycle::total 43870869 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.iq.fu_full::IntAlu 27565 2.58% 2.58% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 466 0.04% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.62% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 837939 78.44% 81.06% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 202337 18.94% 100.00% # attempts to use FU when none available
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 20407 0.05% 0.05% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 22494595 59.60% 59.66% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 50051 0.13% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.79% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 9563453 25.34% 85.13% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 5610668 14.87% 100.00% # Type of FU issued
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.iq.FU_type_0::total 37739879 # Type of FU issued
system.cpu0.iq.rate 0.570847 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 1068307 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.028307 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 120546534 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 44606042 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 34820056 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 8333 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 4740 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 38783456 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 4323 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 326383 # Number of loads that had data forwarded from stores
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.iew.lsq.thread0.squashedLoads 1507630 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 4080 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 13930 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 608245 # Number of stores squashed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 2149509 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 5404 # Number of times an access to memory failed due to the cache being blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.iew.iewSquashCycles 1056312 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 4064319 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 129740 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 38471177 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 88757 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 7928571 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 5881726 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 461616 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 49674 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 17745 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 13930 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 159357 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 144737 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 304094 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 37337331 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 9402148 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 402548 # Number of squashed instructions skipped in execute
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.iew.exec_nop 138361 # number of nop insts executed
system.cpu0.iew.exec_refs 14958639 # number of memory reference insts executed
system.cpu0.iew.exec_branches 4921687 # Number of branches executed
system.cpu0.iew.exec_stores 5556491 # Number of stores executed
system.cpu0.iew.exec_rate 0.564758 # Inst execution rate
system.cpu0.iew.wb_sent 37117116 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 34823949 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 18360594 # num instructions producing a value
system.cpu0.iew.wb_consumers 34980725 # num instructions consuming a value
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.iew.wb_rate 0.526741 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.524877 # average fanout of values written-back
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.commit.commitCommittedInsts 24134633 # The number of committed instructions
system.cpu0.commit.commitCommittedOps 31866160 # The number of committed instructions
system.cpu0.commit.commitSquashedInsts 6466683 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 656866 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 267750 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 42850944 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.743651 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.697776 # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.commit.committed_per_cycle::0 30739496 71.74% 71.74% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 6075340 14.18% 85.91% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 1944692 4.54% 90.45% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 1041937 2.43% 92.88% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 773699 1.81% 94.69% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 503770 1.18% 95.86% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 405337 0.95% 96.81% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 203427 0.47% 97.29% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1163246 2.71% 100.00% # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.commit.committed_per_cycle::total 42850944 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 24134633 # Number of instructions committed
system.cpu0.commit.committedOps 31866160 # Number of ops (including micro ops) committed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.commit.refs 11694422 # Number of memory references committed
system.cpu0.commit.loads 6420941 # Number of loads committed
system.cpu0.commit.membars 234529 # Number of memory barriers committed
system.cpu0.commit.branches 4382702 # Number of branches committed
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 28193395 # Number of committed integer instructions.
system.cpu0.commit.function_calls 499856 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 1163246 # number cycles where commit BW limit reached
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.rob.rob_reads 79207972 # The number of ROB reads
system.cpu0.rob.rob_writes 77724528 # The number of ROB writes
system.cpu0.timesIdled 427936 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 22241224 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 5096899290 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 24053891 # Number of Instructions Simulated
system.cpu0.committedOps 31785418 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 24053891 # Number of Instructions Simulated
system.cpu0.cpi 2.748499 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 2.748499 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.363835 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.363835 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 174526329 # number of integer regfile reads
system.cpu0.int_regfile_writes 34331240 # number of integer regfile writes
system.cpu0.fp_regfile_reads 3280 # number of floating regfile reads
system.cpu0.fp_regfile_writes 898 # number of floating regfile writes
system.cpu0.misc_regfile_reads 46875879 # number of misc regfile reads
system.cpu0.misc_regfile_writes 527497 # number of misc regfile writes
system.cpu0.icache.replacements 406974 # number of replacements
system.cpu0.icache.tagsinuse 511.614338 # Cycle average of tags in use
system.cpu0.icache.total_refs 3978434 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 407486 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 9.763364 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 6469268000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 511.614338 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.999247 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.999247 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 3978434 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 3978434 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 3978434 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 3978434 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 3978434 # number of overall hits
system.cpu0.icache.overall_hits::total 3978434 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 441298 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 441298 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 441298 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 441298 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 441298 # number of overall misses
system.cpu0.icache.overall_misses::total 441298 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7186656997 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 7186656997 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 7186656997 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 7186656997 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 7186656997 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 7186656997 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 4419732 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 4419732 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 4419732 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 4419732 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 4419732 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 4419732 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099847 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.099847 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099847 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.099847 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099847 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.099847 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16285.269811 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 16285.269811 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16285.269811 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 16285.269811 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16285.269811 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 16285.269811 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 1454497 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.icache.blocked::no_mshrs 171 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 8505.830409 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.icache.writebacks::writebacks 29234 # number of writebacks
system.cpu0.icache.writebacks::total 29234 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33802 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 33802 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 33802 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 33802 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 33802 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 33802 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407496 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 407496 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 407496 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 407496 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 407496 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 407496 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5527499503 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 5527499503 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5527499503 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 5527499503 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5527499503 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 5527499503 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8379000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8379000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8379000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 8379000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092199 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.092199 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.092199 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13564.549107 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13564.549107 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13564.549107 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.dcache.replacements 275761 # number of replacements
system.cpu0.dcache.tagsinuse 476.305820 # Cycle average of tags in use
system.cpu0.dcache.total_refs 9551525 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 276273 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 34.572778 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 51448000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.occ_blocks::cpu0.data 476.305820 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.930285 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.930285 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 5934693 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 5934693 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3224707 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 3224707 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174478 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 174478 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171499 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 171499 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 9159400 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 9159400 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 9159400 # number of overall hits
system.cpu0.dcache.overall_hits::total 9159400 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 401255 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 401255 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1594245 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1594245 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9007 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 9007 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7794 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 7794 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1995500 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1995500 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1995500 # number of overall misses
system.cpu0.dcache.overall_misses::total 1995500 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7289566500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 7289566500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71816395371 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 71816395371 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 114642500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 114642500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 93715000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 93715000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 79105961871 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 79105961871 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 79105961871 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 79105961871 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6335948 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 6335948 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4818952 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4818952 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183485 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 183485 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179293 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 179293 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 11154900 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 11154900 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 11154900 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 11154900 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063330 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.063330 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330828 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.330828 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049088 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.049088 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043471 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043471 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178890 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.178890 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178890 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.178890 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18166.917546 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 18166.917546 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45047.276530 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 45047.276530 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12728.155879 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12728.155879 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12023.992815 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12023.992815 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39642.175831 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 39642.175831 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39642.175831 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 39642.175831 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 7140493 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 1629000 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 1441 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 89 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4955.234559 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 18303.370787 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.dcache.writebacks::writebacks 255942 # number of writebacks
system.cpu0.dcache.writebacks::total 255942 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211815 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 211815 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463184 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1463184 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 509 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 509 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1674999 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1674999 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1674999 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1674999 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189440 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 189440 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131061 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 131061 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8498 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8498 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7791 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7791 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 320501 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 320501 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 320501 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 320501 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2806583905 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2806583905 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4685193022 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4685193022 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 80265007 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 80265007 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 69214057 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 69214057 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7491776927 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 7491776927 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7491776927 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 7491776927 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10315161000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10315161000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 849550399 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 849550399 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11164711399 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11164711399 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029899 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029899 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027197 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027197 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046314 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046314 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043454 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043454 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028732 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.028732 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028732 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.028732 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14815.159971 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14815.159971 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35748.186127 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35748.186127 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9445.164392 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9445.164392 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8883.847645 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8883.847645 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23375.206090 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23375.206090 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23375.206090 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23375.206090 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.dtb.read_hits 43446349 # DTB read hits
system.cpu1.dtb.read_misses 46684 # DTB read misses
system.cpu1.dtb.write_hits 7088138 # DTB write hits
system.cpu1.dtb.write_misses 12274 # DTB write misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.dtb.flush_entries 2545 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 3731 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 361 # Number of TLB faults due to prefetch
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.dtb.perms_faults 673 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 43493033 # DTB read accesses
system.cpu1.dtb.write_accesses 7100412 # DTB write accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.dtb.hits 50534487 # DTB hits
system.cpu1.dtb.misses 58958 # DTB misses
system.cpu1.dtb.accesses 50593445 # DTB accesses
system.cpu1.itb.inst_hits 9221438 # ITB inst hits
system.cpu1.itb.inst_misses 6034 # ITB inst misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.itb.flush_entries 1610 # Number of entries that have been flushed from TLB
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.itb.perms_faults 1730 # Number of TLB faults due to permissions restrictions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.itb.inst_accesses 9227472 # ITB inst accesses
system.cpu1.itb.hits 9221438 # DTB hits
system.cpu1.itb.misses 6034 # DTB misses
system.cpu1.itb.accesses 9227472 # DTB accesses
system.cpu1.numCycles 353824423 # number of cpu cycles simulated
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.BPredUnit.lookups 9470897 # Number of BP lookups
system.cpu1.BPredUnit.condPredicted 7703385 # Number of conditional branches predicted
system.cpu1.BPredUnit.condIncorrect 447489 # Number of conditional branches incorrect
system.cpu1.BPredUnit.BTBLookups 6420671 # Number of BTB lookups
system.cpu1.BPredUnit.BTBHits 5281203 # Number of BTB hits
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.BPredUnit.usedRAS 834152 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 50449 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 22167103 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 70445168 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 9470897 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 6115355 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 14956565 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 4597208 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 88094 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.BlockedCycles 73687570 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 6011 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 61739 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 141755 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 9219303 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 857673 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 3541 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 114241434 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 0.747913 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.114106 # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.fetch.rateDist::0 99293168 86.92% 86.92% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 828706 0.73% 87.64% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 1015866 0.89% 88.53% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 2054648 1.80% 90.33% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 1280264 1.12% 91.45% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 613123 0.54% 91.99% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 2273093 1.99% 93.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 467514 0.41% 94.38% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 6415052 5.62% 100.00% # Number of instructions fetched each cycle (Total)
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.fetch.rateDist::total 114241434 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.026767 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.199096 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 23740446 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 73499308 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 13432186 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 537783 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 3031711 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 1242419 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 102480 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 79700896 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 342426 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 3031711 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 25267828 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 33699109 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 35312301 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 12394168 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 4536317 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 73261010 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 3244 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 714923 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 3281779 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.FullRegisterEvents 33706 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 77426546 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 339504965 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 339445449 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 59516 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 49265102 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 28161444 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 486276 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 420659 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 8155263 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 14019935 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 8605996 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 1069297 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 1521896 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 66318588 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 855610 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 90596015 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 108958 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 18341957 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 53651445 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 163223 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 114241434 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.793022 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.525613 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.iq.issued_per_cycle::0 83094748 72.74% 72.74% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 8828314 7.73% 80.46% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 4518450 3.96% 84.42% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 3737052 3.27% 87.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 10664138 9.33% 97.02% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1972512 1.73% 98.75% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 1063413 0.93% 99.68% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 282401 0.25% 99.93% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 80406 0.07% 100.00% # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.iq.issued_per_cycle::total 114241434 # Number of insts issued each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.iq.fu_full::IntAlu 29108 0.37% 0.37% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 993 0.01% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 7574349 95.84% 96.22% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 298565 3.78% 100.00% # attempts to use FU when none available
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.iq.FU_type_0::No_OpClass 86745 0.10% 0.10% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 38337785 42.32% 42.41% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 61539 0.07% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 4 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 1698 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.48% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 44639306 49.27% 91.76% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 7468915 8.24% 100.00% # Type of FU issued
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.iq.FU_type_0::total 90596015 # Type of FU issued
system.cpu1.iq.rate 0.256048 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 7903015 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.087234 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 303489486 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 85529327 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 54443530 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 14763 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 8091 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 6830 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 98404572 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 7713 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 368848 # Number of loads that had data forwarded from stores
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.iew.lsq.thread0.squashedLoads 4030694 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 6909 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 21919 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 1587988 # Number of stores squashed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 31965710 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 1045299 # Number of times an access to memory failed due to the cache being blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.iew.iewSquashCycles 3031711 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 25598263 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 405605 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 67299344 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 135063 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 14019935 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 8605996 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 545729 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 81019 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 7196 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 21919 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 232087 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 197105 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 429192 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 87765278 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 43831578 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 2830737 # Number of squashed instructions skipped in execute
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.iew.exec_nop 125146 # number of nop insts executed
system.cpu1.iew.exec_refs 51224987 # number of memory reference insts executed
system.cpu1.iew.exec_branches 7024509 # Number of branches executed
system.cpu1.iew.exec_stores 7393409 # Number of stores executed
system.cpu1.iew.exec_rate 0.248048 # Inst execution rate
system.cpu1.iew.wb_sent 86598496 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 54450360 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 30044182 # num instructions producing a value
system.cpu1.iew.wb_consumers 53342809 # num instructions consuming a value
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.iew.wb_rate 0.153891 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.563228 # average fanout of values written-back
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.commit.commitCommittedInsts 38036954 # The number of committed instructions
system.cpu1.commit.commitCommittedOps 48396972 # The number of committed instructions
system.cpu1.commit.commitSquashedInsts 18817114 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 692387 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 376510 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 111258144 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.434997 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.402953 # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.commit.committed_per_cycle::0 94210177 84.68% 84.68% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 8524716 7.66% 92.34% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 2208233 1.98% 94.32% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 1307974 1.18% 95.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1064973 0.96% 96.46% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 589982 0.53% 96.99% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 1003368 0.90% 97.89% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 487910 0.44% 98.33% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 1860811 1.67% 100.00% # Number of insts commited each cycle
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.commit.committed_per_cycle::total 111258144 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 38036954 # Number of instructions committed
system.cpu1.commit.committedOps 48396972 # Number of ops (including micro ops) committed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.commit.refs 17007249 # Number of memory references committed
system.cpu1.commit.loads 9989241 # Number of loads committed
system.cpu1.commit.membars 202226 # Number of memory barriers committed
system.cpu1.commit.branches 5993368 # Number of branches committed
system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 43235909 # Number of committed integer instructions.
system.cpu1.commit.function_calls 556157 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 1860811 # number cycles where commit BW limit reached
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.rob.rob_reads 175585773 # The number of ROB reads
system.cpu1.rob.rob_writes 137553768 # The number of ROB writes
system.cpu1.timesIdled 1520299 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 239582989 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 4808538839 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 37967315 # Number of Instructions Simulated
system.cpu1.committedOps 48327333 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 37967315 # Number of Instructions Simulated
system.cpu1.cpi 9.319185 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 9.319185 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.107306 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.107306 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 393921761 # number of integer regfile reads
system.cpu1.int_regfile_writes 56840694 # number of integer regfile writes
system.cpu1.fp_regfile_reads 4925 # number of floating regfile reads
system.cpu1.fp_regfile_writes 2334 # number of floating regfile writes
system.cpu1.misc_regfile_reads 90313719 # number of misc regfile reads
system.cpu1.misc_regfile_writes 429414 # number of misc regfile writes
system.cpu1.icache.replacements 622931 # number of replacements
system.cpu1.icache.tagsinuse 498.760560 # Cycle average of tags in use
system.cpu1.icache.total_refs 8545880 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 623443 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 13.707556 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 74633827000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.occ_blocks::cpu1.inst 498.760560 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.974142 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.974142 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 8545880 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 8545880 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 8545880 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 8545880 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 8545880 # number of overall hits
system.cpu1.icache.overall_hits::total 8545880 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 673372 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 673372 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 673372 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 673372 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 673372 # number of overall misses
system.cpu1.icache.overall_misses::total 673372 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10716931993 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 10716931993 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 10716931993 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 10716931993 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 10716931993 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 10716931993 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 9219252 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 9219252 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 9219252 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 9219252 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 9219252 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 9219252 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073040 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.073040 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073040 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.073040 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073040 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.073040 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15915.321684 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 15915.321684 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15915.321684 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 15915.321684 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15915.321684 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 15915.321684 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 1332494 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.icache.blocked::no_mshrs 205 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.icache.avg_blocked_cycles::no_mshrs 6499.970732 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.icache.writebacks::writebacks 33068 # number of writebacks
system.cpu1.icache.writebacks::total 33068 # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49906 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 49906 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 49906 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 49906 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 49906 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 49906 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 623466 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 623466 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 623466 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 623466 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 623466 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 623466 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8227032008 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 8227032008 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8227032008 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 8227032008 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8227032008 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 8227032008 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3154000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3154000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3154000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 3154000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067627 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.067627 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.067627 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13195.638588 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13195.638588 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13195.638588 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.dcache.replacements 362729 # number of replacements
system.cpu1.dcache.tagsinuse 487.126779 # Cycle average of tags in use
system.cpu1.dcache.total_refs 13112337 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 363073 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 36.114878 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 70483759000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 487.126779 # Average occupied blocks per requestor
system.cpu1.dcache.occ_percent::cpu1.data 0.951419 # Average percentage of cache occupancy
system.cpu1.dcache.occ_percent::total 0.951419 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 8613908 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 8613908 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 4252702 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 4252702 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105106 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 105106 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100709 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 100709 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 12866610 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 12866610 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 12866610 # number of overall hits
system.cpu1.dcache.overall_hits::total 12866610 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 410185 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 410185 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 1595357 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 1595357 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14278 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 14278 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10900 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 10900 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 2005542 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 2005542 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 2005542 # number of overall misses
system.cpu1.dcache.overall_misses::total 2005542 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8114216000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 8114216000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66620735237 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 66620735237 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166584000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 166584000 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 94819000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 94819000 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 74734951237 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 74734951237 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 74734951237 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 74734951237 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 9024093 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 9024093 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 5848059 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 5848059 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 119384 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 119384 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111609 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 111609 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 14872152 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 14872152 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 14872152 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 14872152 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045454 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.045454 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272801 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.272801 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119597 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119597 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097662 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097662 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134852 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.134852 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134852 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.134852 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19781.844777 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 19781.844777 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41759.139326 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 41759.139326 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11667.180277 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11667.180277 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8698.990826 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8698.990826 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 37264.216475 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 37264.216475 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 37264.216475 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 37264.216475 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 29196505 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 5606000 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 6645 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 174 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4393.755455 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 32218.390805 # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.dcache.writebacks::writebacks 327467 # number of writebacks
system.cpu1.dcache.writebacks::total 327467 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 179191 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 179191 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432552 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 1432552 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1457 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1457 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 1611743 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 1611743 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 1611743 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 1611743 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 230994 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 230994 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162805 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 162805 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12821 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12821 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10892 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 10892 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 393799 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 393799 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 393799 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 393799 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3545762451 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3545762451 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5565749199 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5565749199 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104395505 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104395505 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60832506 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60832506 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9111511650 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 9111511650 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9111511650 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 9111511650 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137004750500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137004750500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40571899654 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40571899654 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 177576650154 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 177576650154 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025597 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027839 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027839 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107393 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107393 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097591 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097591 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026479 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.026479 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026479 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.026479 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15350.019702 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15350.019702 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34186.598686 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34186.598686 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8142.539973 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8142.539973 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5585.062982 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5585.062982 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23137.467718 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23137.467718 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23137.467718 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23137.467718 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_refs nan # Average number of references to valid blocks.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305278151135 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1305278151135 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305278151135 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1305278151135 # number of overall MSHR uncacheable cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu0.kern.inst.quiesce 43785 # number of quiesce instructions executed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu1.kern.inst.quiesce 53912 # number of quiesce instructions executed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink