2008-11-10 06:57:15 +01:00
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|
---------- Begin Simulation Statistics ----------
|
2012-10-30 14:35:32 +01:00
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|
|
sim_seconds 0.365989 # Number of seconds simulated
|
2012-12-30 19:45:52 +01:00
|
|
|
sim_ticks 365989064000 # Number of ticks simulated
|
|
|
|
|
final_tick 365989064000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
2012-01-10 16:59:01 +01:00
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|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
2013-01-24 19:29:00 +01:00
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|
|
host_inst_rate 496442 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_op_rate 874155 # Simulator op (including micro ops) rate (op/s)
|
|
|
|
|
host_tick_rate 1150035399 # Simulator tick rate (ticks/s)
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|
|
|
|
host_mem_usage 428932 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 318.24 # Real time elapsed on the host
|
2012-08-15 16:38:05 +02:00
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|
|
sim_insts 157988548 # Number of instructions simulated
|
2012-12-30 19:45:52 +01:00
|
|
|
sim_ops 278192464 # Number of ops (including micro ops) simulated
|
2012-10-30 14:35:32 +01:00
|
|
|
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
|
|
|
|
|
system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory
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|
|
|
|
system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory
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|
|
|
|
system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory
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|
|
|
|
system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory
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|
|
|
|
system.physmem.bytes_written::writebacks 6400 # Number of bytes written to this memory
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|
|
|
|
system.physmem.bytes_written::total 6400 # Number of bytes written to this memory
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|
|
|
|
system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory
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|
|
|
|
system.physmem.num_reads::cpu.data 29246 # Number of read requests responded to by this memory
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|
|
|
|
system.physmem.num_reads::total 30049 # Number of read requests responded to by this memory
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|
|
|
|
system.physmem.num_writes::writebacks 100 # Number of write requests responded to by this memory
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|
|
|
|
system.physmem.num_writes::total 100 # Number of write requests responded to by this memory
|
|
|
|
|
system.physmem.bw_read::cpu.inst 140419 # Total read bandwidth from this memory (bytes/s)
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|
|
|
|
system.physmem.bw_read::cpu.data 5114207 # Total read bandwidth from this memory (bytes/s)
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|
|
|
|
system.physmem.bw_read::total 5254627 # Total read bandwidth from this memory (bytes/s)
|
|
|
|
|
system.physmem.bw_inst_read::cpu.inst 140419 # Instruction read bandwidth from this memory (bytes/s)
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|
|
|
|
system.physmem.bw_inst_read::total 140419 # Instruction read bandwidth from this memory (bytes/s)
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|
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|
|
system.physmem.bw_write::writebacks 17487 # Write bandwidth from this memory (bytes/s)
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|
|
|
|
system.physmem.bw_write::total 17487 # Write bandwidth from this memory (bytes/s)
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|
|
|
|
system.physmem.bw_total::writebacks 17487 # Total bandwidth to/from this memory (bytes/s)
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|
|
|
|
system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s)
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|
|
|
|
system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s)
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|
|
|
|
system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.workload.num_syscalls 444 # Number of system calls
|
2012-12-30 19:45:52 +01:00
|
|
|
system.cpu.numCycles 731978128 # number of cpu cycles simulated
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.committedInsts 157988548 # Number of instructions committed
|
2012-12-30 19:45:52 +01:00
|
|
|
system.cpu.committedOps 278192464 # Number of ops (including micro ops) committed
|
|
|
|
|
system.cpu.num_int_alu_accesses 278186173 # Number of integer alu accesses
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
|
|
|
|
|
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
|
2012-12-30 19:45:52 +01:00
|
|
|
system.cpu.num_int_insts 278186173 # number of integer instructions
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.num_fp_insts 40 # number of float instructions
|
2012-12-30 19:45:52 +01:00
|
|
|
system.cpu.num_int_register_reads 739519998 # number of times the integer registers were read
|
|
|
|
|
system.cpu.num_int_register_writes 279212719 # number of times the integer registers were written
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
|
|
|
|
|
system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
|
2012-12-30 19:45:52 +01:00
|
|
|
system.cpu.num_mem_refs 122219136 # number of memory refs
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.num_load_insts 90779384 # Number of load instructions
|
2012-12-30 19:45:52 +01:00
|
|
|
system.cpu.num_store_insts 31439752 # Number of store instructions
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
2012-12-30 19:45:52 +01:00
|
|
|
system.cpu.num_busy_cycles 731978128 # Number of busy cycles
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
|
|
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
|
|
|
|
system.cpu.icache.replacements 24 # number of replacements
|
2012-12-30 19:45:52 +01:00
|
|
|
system.cpu.icache.tagsinuse 665.632509 # Cycle average of tags in use
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.icache.total_refs 217695357 # Total number of references to valid blocks.
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.icache.avg_refs 269424.946782 # Average number of references to valid blocks.
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-12-30 19:45:52 +01:00
|
|
|
system.cpu.icache.occ_blocks::cpu.inst 665.632509 # Average occupied blocks per requestor
|
2012-10-15 14:09:54 +02:00
|
|
|
system.cpu.icache.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_percent::total 0.325016 # Average percentage of cache occupancy
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_hits::total 217695357 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits::cpu.inst 217695357 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_hits::total 217695357 # number of overall hits
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_misses::total 808 # number of overall misses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles
|
2012-08-15 16:38:05 +02:00
|
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 217696165 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses::total 217696165 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses::cpu.inst 217696165 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_accesses::total 217696165 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::cpu.inst 217696165 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses::total 217696165 # number of overall (read+write) accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total 54740.099010 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total 54740.099010 # average overall miss latency
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42614000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 42614000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42614000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency::total 42614000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42614000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency::total 42614000 # number of overall MSHR miss cycles
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.replacements 318 # number of replacements
|
2012-12-30 19:45:52 +01:00
|
|
|
system.cpu.l2cache.tagsinuse 20041.899820 # Cycle average of tags in use
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 30026 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 132.965397 # Average number of references to valid blocks.
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2012-12-30 19:45:52 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::writebacks 19330.353217 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 557.646383 # Average occupied blocks per requestor
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.occ_blocks::cpu.data 153.900220 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.l2cache.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::total 0.611630 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::writebacks 2062484 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits::total 2062484 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::cpu.data 2037583 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_hits::total 2037588 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::cpu.data 2037583 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_hits::total 2037588 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 222 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses::total 1025 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 29024 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses::total 29024 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::cpu.data 29246 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_misses::total 30049 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_misses::total 30049 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41756000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11544000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 53300000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509279000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1509279000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 41756000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 1520823000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency::total 1562579000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 41756000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 1520823000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency::total 1562579000 # number of overall miss cycles
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses)
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 2062484 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses::total 2062484 # number of Writeback accesses(hits+misses)
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 808 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2066829 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_accesses::total 2067637 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 808 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2066829 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses::total 2067637 # number of overall (read+write) accesses
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993812 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000113 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.000523 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.273530 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.273530 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993812 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.014150 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate::total 0.014533 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.068082 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.068082 # average ReadExReq miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52001.031648 # average overall miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52001.031648 # average overall miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2012-05-09 20:52:14 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2008-11-10 06:57:15 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2012-10-30 14:35:32 +01:00
|
|
|
system.cpu.l2cache.writebacks::writebacks 100 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.writebacks::total 100 # number of writebacks
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 803 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29024 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 29024 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 803 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 29246 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses::total 30049 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32120000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8880000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41000000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1160960000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1160960000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32120000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1169840000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1201960000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32120000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1169840000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1201960000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
2012-02-12 23:07:43 +01:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
2012-06-05 07:23:16 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
2012-01-10 16:59:01 +01:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2013-01-24 19:29:00 +01:00
|
|
|
system.cpu.dcache.replacements 2062733 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 4076.488630 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 120152369 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.warmup_cycle 126079700000 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.occ_blocks::cpu.data 4076.488630 # Average occupied blocks per requestor
|
|
|
|
|
system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits
|
|
|
|
|
system.cpu.dcache.demand_hits::cpu.data 120152369 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_hits::total 120152369 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits::cpu.data 120152369 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_hits::total 120152369 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.demand_accesses::cpu.data 122219198 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_accesses::total 122219198 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::cpu.data 122219198 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses::total 122219198 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks
|
|
|
|
|
system.cpu.dcache.writebacks::total 2062484 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2008-11-10 06:57:15 +01:00
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---------- End Simulation Statistics ----------
|
