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gem5/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt

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config file updates --HG-- extra : convert_revision : b873e0b436d71d86b87b8d9df7115bcc7ceb2b50
2006-10-12 21:04:14 +02:00
---------- Begin Simulation Statistics ----------
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
sim_seconds 0.023378 # Number of seconds simulated
sim_ticks 23378067000 # Number of ticks simulated
final_tick 23378067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
host_inst_rate 166789 # Simulator instruction rate (inst/s)
host_op_rate 166789 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 46320112 # Simulator tick rate (ticks/s)
host_mem_usage 219224 # Number of bytes of host memory used
host_seconds 504.71 # Real time elapsed on the host
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
sim_insts 84179709 # Number of instructions simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sim_ops 84179709 # Number of ops (including micro ops) simulated
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.bytes_read::cpu.inst 196096 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 138496 # Number of bytes read from this memory
system.physmem.bytes_read::total 334592 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 196096 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 196096 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3064 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2164 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 8388033 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 5924185 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14312218 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 8388033 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 8388033 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 8388033 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5924185 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 14312218 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 5228 # Total number of read requests seen
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeReqs 0 # Total number of write requests seen
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.cpureqs 5228 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 334592 # Total number of bytes read from memory
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bytesWritten 0 # Total number of bytes written to memory
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.bytesConsumedRd 334592 # bytesRead derated as per pkt->getSize()
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.perBankRdReqs::0 367 # Track reads on a per bank basis
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.perBankRdReqs::1 340 # Track reads on a per bank basis
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.perBankRdReqs::2 253 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 316 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 255 # Track reads on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.perBankRdReqs::5 295 # Track reads on a per bank basis
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.perBankRdReqs::6 373 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 401 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 320 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 300 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 275 # Track reads on a per bank basis
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.perBankRdReqs::11 288 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 326 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 385 # Track reads on a per bank basis
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.perBankRdReqs::14 382 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 352 # Track reads on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.totGap 23377961000 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.readPktSize::6 5228 # Categorize read packet sizes
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.rdQLenPdf::0 3190 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1567 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 365 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::3 92 # What read queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.totQLat 21787213 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 116311213 # Sum of mem lat for all requests
system.physmem.totBusLat 20912000 # Total cycles spent in databus access
system.physmem.totBankLat 73612000 # Total cycles spent in bank access
system.physmem.avgQLat 4167.41 # Average queueing delay per request
system.physmem.avgBankLat 14080.34 # Average bank access latency per request
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgBusLat 4000.00 # Average bus latency per request
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.avgMemAccLat 22247.75 # Average memory access latency
system.physmem.avgRdBW 14.31 # Average achieved read bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.avgConsumedRdBW 14.31 # Average consumed read bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.09 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.readRowHits 4677 # Number of row buffer hits during reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.physmem.avgGap 4471683.44 # Average gap between requests
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dtb.read_hits 23102664 # DTB read hits
system.cpu.dtb.read_misses 192481 # DTB read misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.dtb.read_acv 2 # DTB read access violations
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dtb.read_accesses 23295145 # DTB read accesses
system.cpu.dtb.write_hits 7068005 # DTB write hits
system.cpu.dtb.write_misses 1092 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 7069097 # DTB write accesses
system.cpu.dtb.data_hits 30170669 # DTB hits
system.cpu.dtb.data_misses 193573 # DTB misses
system.cpu.dtb.data_acv 2 # DTB access violations
system.cpu.dtb.data_accesses 30364242 # DTB accesses
system.cpu.itb.fetch_hits 14708082 # ITB hits
system.cpu.itb.fetch_misses 96 # ITB misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.itb.fetch_acv 0 # ITB acv
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.itb.fetch_accesses 14708178 # ITB accesses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.numCycles 46756135 # number of cpu cycles simulated
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.BPredUnit.lookups 14833517 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 10762267 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 917019 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 8075874 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 6944735 # Number of BTB hits
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.BPredUnit.usedRAS 1466052 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 3147 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 15430530 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 126815242 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14833517 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 8410787 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 22106787 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4454905 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 5569972 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 2009 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 14708082 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 322729 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 46612836 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.720608 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.376239 # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.fetch.rateDist::0 24506049 52.57% 52.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 2362426 5.07% 57.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1191299 2.56% 60.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 1739407 3.73% 63.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2752944 5.91% 69.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1147923 2.46% 72.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1216668 2.61% 74.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 768362 1.65% 76.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 10927758 23.44% 100.00% # Number of instructions fetched each cycle (Total)
tests: stats outputs now include CDFs, update tests that use those so they're easier to diff
2009-07-07 00:49:48 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.fetch.rateDist::total 46612836 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.317253 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.712270 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 17256308 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 4263506 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 20503237 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 1097959 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3491826 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 2511850 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 12028 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 123858190 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 32546 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 3491826 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 18399179 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 964925 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 7287 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 20435541 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 3314078 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 121046582 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 48 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 399182 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 2434828 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 88894409 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 157311905 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 147648223 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 9663682 # Number of floating rename lookups
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.rename.UndoneMaps 20467048 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 739 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 732 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 8795383 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 25343096 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 8237940 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 2594464 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 920924 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 105370947 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1446 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 96530679 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 178191 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 20721356 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 15565520 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1057 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 46612836 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.070903 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.875751 # Number of insts issued each cycle
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.issued_per_cycle::0 12074665 25.90% 25.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 9351108 20.06% 45.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 8402793 18.03% 63.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 6288710 13.49% 77.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 4905546 10.52% 88.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2859533 6.13% 94.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1729691 3.71% 97.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 796460 1.71% 99.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 204330 0.44% 100.00% # Number of insts issued each cycle
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.issued_per_cycle::total 46612836 # Number of insts issued each cycle
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.fu_full::IntAlu 190047 12.12% 12.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 12.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 12.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 203 0.01% 12.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 7055 0.45% 12.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 5882 0.38% 12.95% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 842974 53.75% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.70% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 444058 28.31% 95.01% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 78249 4.99% 100.00% # attempts to use FU when none available
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.FU_type_0::IntAlu 58717725 60.83% 60.83% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 479593 0.50% 61.32% # Type of FU issued
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.FU_type_0::FloatAdd 2796739 2.90% 64.22% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 115257 0.12% 64.34% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 2386885 2.47% 66.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 311006 0.32% 67.14% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 760000 0.79% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 23812199 24.67% 92.59% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 7150949 7.41% 100.00% # Type of FU issued
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.FU_type_0::total 96530679 # Type of FU issued
system.cpu.iq.rate 2.064556 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1568468 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.016248 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 226318050 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 117401953 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 87051166 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 15102803 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 8726703 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 7059295 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 90117667 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7981473 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1519109 # Number of loads that had data forwarded from stores
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 5346898 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 18469 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 35032 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1736837 # Number of stores squashed
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 10557 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.iewSquashCycles 3491826 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 132020 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 18316 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 115597875 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 364987 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 25343096 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 8237940 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1446 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3142 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 30 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 35032 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 529110 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 494336 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1023446 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 95309066 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 23295605 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1221613 # Number of squashed instructions skipped in execute
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.exec_nop 10225482 # number of nop insts executed
system.cpu.iew.exec_refs 30364899 # number of memory reference insts executed
system.cpu.iew.exec_branches 12021435 # Number of branches executed
system.cpu.iew.exec_stores 7069294 # Number of stores executed
system.cpu.iew.exec_rate 2.038429 # Inst execution rate
system.cpu.iew.wb_sent 94627849 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 94110461 # cumulative count of insts written-back
system.cpu.iew.wb_producers 64468484 # num instructions producing a value
system.cpu.iew.wb_consumers 89853069 # num instructions consuming a value
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iew.wb_rate 2.012794 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.717488 # average fanout of values written-back
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.commitSquashedInsts 23695922 # The number of squashed insts skipped by commit
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.branchMispredicts 905358 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 43121010 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.131283 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.747044 # Number of insts commited each cycle
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.committed_per_cycle::0 16684738 38.69% 38.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 9903892 22.97% 61.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 4485087 10.40% 72.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2259914 5.24% 77.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1605498 3.72% 81.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1123100 2.60% 83.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 719913 1.67% 85.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 818667 1.90% 87.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5520201 12.80% 100.00% # Number of insts commited each cycle
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.committed_per_cycle::total 43121010 # Number of insts commited each cycle
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.commit.committedInsts 91903055 # Number of instructions committed
system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 26497301 # Number of memory references committed
system.cpu.commit.loads 19996198 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 10240685 # Number of branches committed
system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions.
system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
system.cpu.commit.function_calls 1029620 # Number of function calls committed.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.commit.bw_lim_events 5520201 # number cycles where commit BW limit reached
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.rob.rob_reads 153198746 # The number of ROB reads
system.cpu.rob.rob_writes 234713539 # The number of ROB writes
system.cpu.timesIdled 5103 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 143299 # Total number of cycles that the CPU has spent unscheduled due to idling
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.cpi 0.555432 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.555432 # CPI: Total CPI of All Threads
system.cpu.ipc 1.800399 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.800399 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 129015669 # number of integer regfile reads
system.cpu.int_regfile_writes 70499119 # number of integer regfile writes
system.cpu.fp_regfile_reads 6185969 # number of floating regfile reads
system.cpu.fp_regfile_writes 6040722 # number of floating regfile writes
system.cpu.misc_regfile_reads 714490 # number of misc regfile reads
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.icache.replacements 9535 # number of replacements
system.cpu.icache.tagsinuse 1597.711655 # Cycle average of tags in use
system.cpu.icache.total_refs 14694095 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 11468 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1281.312783 # Average number of references to valid blocks.
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.icache.occ_blocks::cpu.inst 1597.711655 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.780133 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.780133 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 14694095 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 14694095 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 14694095 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 14694095 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 14694095 # number of overall hits
system.cpu.icache.overall_hits::total 14694095 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 13987 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 13987 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 13987 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 13987 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 13987 # number of overall misses
system.cpu.icache.overall_misses::total 13987 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 308160500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 308160500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 308160500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 308160500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 308160500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 308160500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 14708082 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 14708082 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 14708082 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 14708082 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 14708082 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 14708082 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000951 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000951 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000951 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000951 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000951 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000951 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22031.922499 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22031.922499 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22031.922499 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22031.922499 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22031.922499 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22031.922499 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 97 # number of cycles access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 19.400000 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2519 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 2519 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 2519 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 2519 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2519 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2519 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11468 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 11468 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 11468 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 11468 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 11468 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 11468 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 234957500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 234957500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 234957500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 234957500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 234957500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 234957500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000780 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000780 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000780 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000780 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000780 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000780 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20488.097314 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20488.097314 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20488.097314 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20488.097314 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20488.097314 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20488.097314 # average overall mshr miss latency
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2411.634709 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8474 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3589 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.361103 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 17.671111 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2014.246310 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 379.717288 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.061470 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.011588 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.073597 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 8404 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 8459 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 109 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 109 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 8404 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 81 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 8485 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 8404 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 81 # number of overall hits
system.cpu.l2cache.overall_hits::total 8485 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3064 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 458 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 3522 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1706 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1706 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3064 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2164 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 5228 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3064 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2164 # number of overall misses
system.cpu.l2cache.overall_misses::total 5228 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 139445500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25445000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 164890500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 80526000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 80526000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 139445500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 105971000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 245416500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 139445500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 105971000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 245416500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11468 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 513 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 11981 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 109 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 109 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1732 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1732 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 11468 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 13713 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 11468 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 13713 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.267178 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.892788 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.293965 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984988 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.984988 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.267178 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.963920 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.381244 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267178 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.963920 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.381244 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 45510.933420 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55556.768559 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 46817.291312 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47201.641266 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47201.641266 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 45510.933420 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 48969.963031 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 46942.712318 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 45510.933420 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 48969.963031 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 46942.712318 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3064 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 3522 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1706 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1706 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3064 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2164 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5228 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3064 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2164 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 100817136 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19709120 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 120526256 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59472062 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59472062 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 100817136 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79181182 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 179998318 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 100817136 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79181182 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 179998318 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.267178 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892788 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.293965 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984988 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984988 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.267178 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963920 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.381244 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267178 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963920 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.381244 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32903.765013 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43033.013100 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34220.969903 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34860.528722 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34860.528722 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32903.765013 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36590.195009 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34429.670620 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32903.765013 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36590.195009 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34429.670620 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 159 # number of replacements
system.cpu.dcache.tagsinuse 1458.941648 # Cycle average of tags in use
system.cpu.dcache.total_refs 28063904 # Total number of references to valid blocks.
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.dcache.sampled_refs 2245 # Sample count of references to valid blocks.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.avg_refs 12500.625390 # Average number of references to valid blocks.
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.occ_blocks::cpu.data 1458.941648 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.356187 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.356187 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 21570663 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21570663 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 6493007 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 6493007 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 234 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 234 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data 28063670 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 28063670 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 28063670 # number of overall hits
system.cpu.dcache.overall_hits::total 28063670 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 977 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 977 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 8096 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 8096 # number of WriteReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.demand_misses::cpu.data 9073 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9073 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9073 # number of overall misses
system.cpu.dcache.overall_misses::total 9073 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 44122000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 44122000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 343188654 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 343188654 # number of WriteReq miss cycles
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 72000 # number of LoadLockedReq miss cycles
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.demand_miss_latency::cpu.data 387310654 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 387310654 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 387310654 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 387310654 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 21571640 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 21571640 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 235 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 28072743 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 28072743 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 28072743 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 28072743 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001245 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001245 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004255 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004255 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000323 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000323 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000323 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000323 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45160.696008 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 45160.696008 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42389.902915 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 42389.902915 # average WriteReq miss latency
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 42688.267828 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 42688.267828 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 42688.267828 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 42688.267828 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 10592 # number of cycles access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.blocked::no_mshrs 468 # number of cycles access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.632479 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.writebacks::writebacks 109 # number of writebacks
system.cpu.dcache.writebacks::total 109 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 465 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6364 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 6364 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 6829 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 6829 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 6829 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 6829 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1732 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1732 # number of WriteReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 2244 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26453500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26453500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82660498 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 82660498 # number of WriteReq MSHR miss cycles
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 70000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 70000 # number of LoadLockedReq MSHR miss cycles
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 109113998 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 109113998 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 109113998 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 109113998 # number of overall MSHR miss cycles
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004255 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004255 # mshr miss rate for LoadLockedReq accesses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51666.992188 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51666.992188 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47725.460739 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47725.460739 # average WriteReq mshr miss latency
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 70000 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 70000 # average LoadLockedReq mshr miss latency
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48624.776292 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 48624.776292 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48624.776292 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 48624.776292 # average overall mshr miss latency
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
config file updates --HG-- extra : convert_revision : b873e0b436d71d86b87b8d9df7115bcc7ceb2b50
2006-10-12 21:04:14 +02:00
---------- End Simulation Statistics ----------
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