2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
2016-07-21 18:19:18 +02:00
sim_seconds 47.296282 # Number of seconds simulated
sim_ticks 47296281748500 # Number of ticks simulated
final_tick 47296281748500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-07-21 18:19:18 +02:00
host_inst_rate 717114 # Simulator instruction rate (inst/s)
host_op_rate 843581 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 34713303168 # Simulator tick rate (ticks/s)
host_mem_usage 688104 # Number of bytes of host memory used
host_seconds 1362.48 # Real time elapsed on the host
sim_insts 977055082 # Number of instructions simulated
sim_ops 1149364510 # Number of ops (including micro ops) simulated
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-07-21 18:19:18 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 151424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 124352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 3875572 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 35081800 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 222336 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 221312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 2647048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 38747248 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 401984 # Number of bytes read from this memory
system.physmem.bytes_read::total 81473076 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 3875572 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 2647048 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6522620 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 101454976 # Number of bytes written to this memory
2015-05-05 09:22:39 +02:00
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
2016-07-21 18:19:18 +02:00
system.physmem.bytes_written::total 101475560 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 2366 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1943 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 100963 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 548166 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 3474 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 3458 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 41467 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 605442 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6281 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1313560 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1585234 # Number of write requests responded to by this memory
2015-05-05 09:22:39 +02:00
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
2016-07-21 18:19:18 +02:00
system.physmem.num_writes::total 1587808 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 3202 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 2629 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 81942 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 741745 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 4701 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 4679 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 55967 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 819245 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8499 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1722611 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 81942 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 55967 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 137910 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2145094 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
2014-12-02 12:08:25 +01:00
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
2016-07-21 18:19:18 +02:00
system.physmem.bw_write::total 2145529 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2145094 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 3202 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 2629 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 81942 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 742181 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 4701 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 4679 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 55967 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 819245 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8499 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3868140 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
2016-07-21 18:19:18 +02:00
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
2014-10-30 05:50:15 +01:00
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-07-21 18:19:18 +02:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 125159 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 125159 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 125159 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 125159 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 125159 # Table walker wait (enqueue to first request) latency
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.walker.walkPageSizes::4K 96412 89.79% 89.79% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 10963 10.21% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 107375 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125159 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125159 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107375 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107375 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 232534 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.read_hits 92471463 # DTB read hits
system.cpu0.dtb.read_misses 88826 # DTB read misses
system.cpu0.dtb.write_hits 85455153 # DTB write hits
system.cpu0.dtb.write_misses 36333 # DTB write misses
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.flush_entries 36431 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.prefetch_faults 4810 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.perms_faults 10399 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 92560289 # DTB read accesses
system.cpu0.dtb.write_accesses 85491486 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
2016-07-21 18:19:18 +02:00
system.cpu0.dtb.hits 177926616 # DTB hits
system.cpu0.dtb.misses 125159 # DTB misses
system.cpu0.dtb.accesses 178051775 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-07-21 18:19:18 +02:00
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 61082 # Table walker walks requested
system.cpu0.itb.walker.walksLong 61082 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples 61082 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 61082 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 61082 # Table walker wait (enqueue to first request) latency
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
2016-07-21 18:19:18 +02:00
system.cpu0.itb.walker.walkPageSizes::4K 54995 98.82% 98.82% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 656 1.18% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 55651 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-07-21 18:19:18 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61082 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61082 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-07-21 18:19:18 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55651 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55651 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 116733 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 496679820 # ITB inst hits
system.cpu0.itb.inst_misses 61082 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-07-21 18:19:18 +02:00
system.cpu0.itb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID
2014-10-30 05:50:15 +01:00
system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
2016-07-21 18:19:18 +02:00
system.cpu0.itb.flush_entries 25177 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
2016-07-21 18:19:18 +02:00
system.cpu0.itb.inst_accesses 496740902 # ITB inst accesses
system.cpu0.itb.hits 496679820 # DTB hits
system.cpu0.itb.misses 61082 # DTB misses
system.cpu0.itb.accesses 496740902 # DTB accesses
system.cpu0.numPwrStateTransitions 26445 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 13222 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 3555001605.490697 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 88683028869.484894 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 3170 23.98% 23.98% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 10025 75.82% 99.80% # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 2 0.02% 99.89% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 7351153278004 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total 13222 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 292050520702 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 47004231227798 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 94592576721 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-10-10 23:45:41 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2016-07-21 18:19:18 +02:00
system.cpu0.kern.inst.quiesce 13223 # number of quiesce instructions executed
system.cpu0.committedInsts 496443686 # Number of instructions committed
system.cpu0.committedOps 583761680 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 535025290 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 524584 # Number of float alu accesses
system.cpu0.num_func_calls 28899937 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 76311856 # number of instructions that are conditional controls
system.cpu0.num_int_insts 535025290 # number of integer instructions
system.cpu0.num_fp_insts 524584 # number of float instructions
system.cpu0.num_int_register_reads 783282318 # number of times the integer registers were read
system.cpu0.num_int_register_writes 424505870 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 845921 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 445948 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 133408683 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 133073326 # number of times the CC registers were written
system.cpu0.num_mem_refs 178027643 # number of memory refs
system.cpu0.num_load_insts 92545018 # Number of load instructions
system.cpu0.num_store_insts 85482625 # Number of store instructions
system.cpu0.num_idle_cycles 94008475597.936935 # Number of idle cycles
system.cpu0.num_busy_cycles 584101123.063064 # Number of busy cycles
system.cpu0.not_idle_fraction 0.006175 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.993825 # Percentage of idle cycles
system.cpu0.Branches 111093071 # Number of branches fetched
2014-10-30 05:50:15 +01:00
system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
2016-07-21 18:19:18 +02:00
system.cpu0.op_class::IntAlu 404699186 69.29% 69.29% # Class of executed instruction
system.cpu0.op_class::IntMult 1236587 0.21% 69.50% # Class of executed instruction
system.cpu0.op_class::IntDiv 60193 0.01% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 72938 0.01% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::MemRead 92545018 15.84% 85.36% # Class of executed instruction
system.cpu0.op_class::MemWrite 85482625 14.64% 100.00% # Class of executed instruction
2014-10-30 05:50:15 +01:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2016-07-21 18:19:18 +02:00
system.cpu0.op_class::total 584096590 # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 6248912 # number of replacements
system.cpu0.dcache.tags.tagsinuse 501.980044 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 171607959 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 6249424 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 27.459804 # Average number of references to valid blocks.
2015-05-05 09:22:39 +02:00
system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
2016-07-21 18:19:18 +02:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.980044 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980430 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.980430 # Average percentage of cache occupancy
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-07-21 18:19:18 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-07-21 18:19:18 +02:00
system.cpu0.dcache.tags.tag_accesses 362271537 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 362271537 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 86024172 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 86024172 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 80672636 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 80672636 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 216269 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 216269 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 261023 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 261023 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2087977 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 2087977 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2051999 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 2051999 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 166957831 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 166957831 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 167174100 # number of overall hits
system.cpu0.dcache.overall_hits::total 167174100 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 3298422 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 3298422 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1479208 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1479208 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 769563 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 769563 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 824176 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 824176 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119749 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 119749 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 154638 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 154638 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 5601806 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 5601806 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 6371369 # number of overall misses
system.cpu0.dcache.overall_misses::total 6371369 # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data 89322594 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 89322594 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 82151844 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 82151844 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 985832 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 985832 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1085199 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1085199 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2207726 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 2207726 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2206637 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 2206637 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 172559637 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 172559637 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 173545469 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 173545469 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036927 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.036927 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018006 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.018006 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.780623 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.780623 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759470 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.759470 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054241 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054241 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.070079 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.070079 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032463 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.032463 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036713 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.036713 # miss rate for overall accesses
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-07-21 18:19:18 +02:00
system.cpu0.dcache.writebacks::writebacks 6248912 # number of writebacks
system.cpu0.dcache.writebacks::total 6248912 # number of writebacks
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 5509619 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.989024 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 491225335 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 5510131 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 89.149484 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 5759898000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989024 # Average occupied blocks per requestor
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-07-21 18:19:18 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-07-21 18:19:18 +02:00
system.cpu0.icache.tags.tag_accesses 998981078 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 998981078 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 491225335 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 491225335 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 491225335 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 491225335 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 491225335 # number of overall hits
system.cpu0.icache.overall_hits::total 491225335 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 5510136 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 5510136 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 5510136 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 5510136 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 5510136 # number of overall misses
system.cpu0.icache.overall_misses::total 5510136 # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst 496735471 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 496735471 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 496735471 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 496735471 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 496735471 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 496735471 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011093 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.011093 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011093 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.011093 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011093 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.011093 # miss rate for overall accesses
2014-10-30 05:50:15 +01:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-07-21 18:19:18 +02:00
system.cpu0.icache.writebacks::writebacks 5509619 # number of writebacks
system.cpu0.icache.writebacks::total 5509619 # number of writebacks
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
2016-07-21 18:19:18 +02:00
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 2653803 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16139.372932 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 15525451 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2669765 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 5.815287 # Average number of references to valid blocks.
2014-12-02 12:08:25 +01:00
system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit.
2016-07-21 18:19:18 +02:00
system.cpu0.l2cache.tags.occ_blocks::writebacks 16063.015838 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 35.657747 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 40.699347 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.980409 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002176 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002484 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.985069 # Average percentage of cache occupancy
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 53 # Occupied blocks per task id
2016-07-21 18:19:18 +02:00
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15909 # Occupied blocks per task id
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id
2016-07-21 18:19:18 +02:00
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1444 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4368 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5335 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4524 # Occupied blocks per task id
2016-05-31 12:07:18 +02:00
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id
2016-07-21 18:19:18 +02:00
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.971008 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 395826781 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 395826781 # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 296735 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 157755 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 454490 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 4439476 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 4439476 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 7317657 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 7317657 # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 746 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 746 # number of UpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 639086 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 639086 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5010934 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 5010934 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2954772 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 2954772 # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 221315 # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total 221315 # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 296735 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 157755 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 5010934 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 3593858 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 9059282 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 296735 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 157755 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 5010934 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 3593858 # number of overall hits
system.cpu0.l2cache.overall_hits::total 9059282 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11441 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8530 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 19971 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 138499 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 138499 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 154638 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 154638 # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 701212 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 701212 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 499202 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 499202 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1232962 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 1232962 # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 602526 # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total 602526 # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11441 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8530 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 499202 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 1934174 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 2453347 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11441 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8530 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 499202 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 1934174 # number of overall misses
system.cpu0.l2cache.overall_misses::total 2453347 # number of overall misses
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 308176 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 166285 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 474461 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4439476 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total 4439476 # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks 7317657 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total 7317657 # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 139245 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 139245 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 154638 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 154638 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1340298 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 1340298 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5510136 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 5510136 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4187734 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 4187734 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 823841 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total 823841 # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 308176 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 166285 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 5510136 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 5528032 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 11512629 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 308176 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 166285 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 5510136 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 5528032 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 11512629 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037125 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.051297 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.042092 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994643 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994643 # miss rate for UpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2016-07-21 18:19:18 +02:00
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.523176 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.523176 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090597 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090597 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294422 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294422 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.731362 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.731362 # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037125 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.051297 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090597 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.349885 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.213101 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037125 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.051297 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090597 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.349885 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.213101 # miss rate for overall accesses
2014-10-30 05:50:15 +01:00
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-07-21 18:19:18 +02:00
system.cpu0.l2cache.writebacks::writebacks 1559963 # number of writebacks
system.cpu0.l2cache.writebacks::total 1559963 # number of writebacks
system.cpu0.toL2Bus.snoop_filter.tot_requests 24176858 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12314856 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1398 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 1775409 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1775098 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 311 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 622617 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 10320487 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 33234 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 33234 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 4439476 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 7319055 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 139245 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 154638 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 293883 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1340298 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1340298 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5510136 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4187734 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 823841 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 823841 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16616141 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19673024 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 364916 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 727936 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 37382017 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 705436820 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753922812 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1459664 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2911744 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 1463731040 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 6082125 # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic 101619328 # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples 30471409 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.066979 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.250027 # Request fanout histogram
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-07-21 18:19:18 +02:00
system.cpu0.toL2Bus.snoop_fanout::0 28430762 93.30% 93.30% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 2040336 6.70% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 311 0.00% 100.00% # Request fanout histogram
2014-10-30 05:50:15 +01:00
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-07-21 18:19:18 +02:00
system.cpu0.toL2Bus.snoop_fanout::total 30471409 # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 144363 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 144363 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walkWaitTime::samples 144363 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 144363 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 144363 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walksPending::samples -274399872 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -274399872 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -274399872 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 111796 88.76% 88.76% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 14154 11.24% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 125950 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144363 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144363 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125950 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125950 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 270313 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.read_hits 90656208 # DTB read hits
system.cpu1.dtb.read_misses 111973 # DTB read misses
system.cpu1.dtb.write_hits 81688076 # DTB write hits
system.cpu1.dtb.write_misses 32390 # DTB write misses
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.flush_entries 44622 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.prefetch_faults 4399 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.perms_faults 11479 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 90768181 # DTB read accesses
system.cpu1.dtb.write_accesses 81720466 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
2016-07-21 18:19:18 +02:00
system.cpu1.dtb.hits 172344284 # DTB hits
system.cpu1.dtb.misses 144363 # DTB misses
system.cpu1.dtb.accesses 172488647 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-07-21 18:19:18 +02:00
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 61351 # Table walker walks requested
system.cpu1.itb.walker.walksLong 61351 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walkWaitTime::samples 61351 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 61351 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 61351 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walksPending::samples -274400872 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -274400872 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -274400872 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 54387 99.05% 99.05% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 524 0.95% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 54911 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-07-21 18:19:18 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61351 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61351 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-07-21 18:19:18 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54911 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54911 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 116262 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 480862179 # ITB inst hits
system.cpu1.itb.inst_misses 61351 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-07-21 18:19:18 +02:00
system.cpu1.itb.flush_tlb_mva_asid 49425 # Number of times TLB was flushed by MVA & ASID
2014-10-30 05:50:15 +01:00
system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
2016-07-21 18:19:18 +02:00
system.cpu1.itb.flush_entries 31395 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
2016-07-21 18:19:18 +02:00
system.cpu1.itb.inst_accesses 480923530 # ITB inst accesses
system.cpu1.itb.hits 480862179 # DTB hits
system.cpu1.itb.misses 61351 # DTB misses
system.cpu1.itb.accesses 480923530 # DTB accesses
system.cpu1.numPwrStateTransitions 12248 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 6124 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 7676898273.449706 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 188572680414.552032 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows 4459 72.81% 72.81% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 1644 26.85% 99.66% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.74% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.80% # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.84% # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu1.pwrStateClkGateDist::overflows 10 0.16% 100.00% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 11813542452500 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total 6124 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 282956721894 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 47013325026606 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 94592569622 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-10-10 23:45:41 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
2016-07-21 18:19:18 +02:00
system.cpu1.kern.inst.quiesce 6124 # number of quiesce instructions executed
system.cpu1.committedInsts 480611396 # Number of instructions committed
system.cpu1.committedOps 565602830 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 519092247 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 374666 # Number of float alu accesses
system.cpu1.num_func_calls 28363152 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 73579507 # number of instructions that are conditional controls
system.cpu1.num_int_insts 519092247 # number of integer instructions
system.cpu1.num_fp_insts 374666 # number of float instructions
system.cpu1.num_int_register_reads 766987939 # number of times the integer registers were read
system.cpu1.num_int_register_writes 413187755 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 609913 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 303136 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 127077975 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 126798720 # number of times the CC registers were written
system.cpu1.num_mem_refs 172465256 # number of memory refs
system.cpu1.num_load_insts 90755131 # Number of load instructions
system.cpu1.num_store_insts 81710125 # Number of store instructions
system.cpu1.num_idle_cycles 94026656141.566330 # Number of idle cycles
system.cpu1.num_busy_cycles 565913480.433670 # Number of busy cycles
system.cpu1.not_idle_fraction 0.005983 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.994017 # Percentage of idle cycles
system.cpu1.Branches 107067845 # Number of branches fetched
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
2016-07-21 18:19:18 +02:00
system.cpu1.op_class::IntAlu 392212619 69.31% 69.31% # Class of executed instruction
system.cpu1.op_class::IntMult 1132978 0.20% 69.51% # Class of executed instruction
system.cpu1.op_class::IntDiv 61173 0.01% 69.52% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 36628 0.01% 69.52% # Class of executed instruction
2016-02-10 10:08:27 +01:00
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction
2016-07-21 18:19:18 +02:00
system.cpu1.op_class::MemRead 90755131 16.04% 85.56% # Class of executed instruction
system.cpu1.op_class::MemWrite 81710125 14.44% 100.00% # Class of executed instruction
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2016-07-21 18:19:18 +02:00
system.cpu1.op_class::total 565908654 # Class of executed instruction
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 5970882 # number of replacements
system.cpu1.dcache.tags.tagsinuse 423.354804 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 166384450 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 5971393 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 27.863591 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8470277781000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 423.354804 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.826865 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.826865 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 350957209 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 350957209 # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 84198599 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 84198599 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 77532107 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 77532107 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187263 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 187263 # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64879 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 64879 # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2055501 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 2055501 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2044925 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 2044925 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 161795585 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 161795585 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 161982848 # number of overall hits
system.cpu1.dcache.overall_hits::total 161982848 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 3367289 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 3367289 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 1465578 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 1465578 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 793623 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 793623 # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 433878 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 433878 # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 147104 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 147104 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 156474 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 156474 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 5266745 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 5266745 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 6060368 # number of overall misses
system.cpu1.dcache.overall_misses::total 6060368 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 87565888 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 87565888 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 78997685 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 78997685 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980886 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 980886 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 498757 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 498757 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2202605 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 2202605 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2201399 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 2201399 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 167062330 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 167062330 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 168043216 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 168043216 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038454 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.038454 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018552 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.018552 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.809088 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.809088 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.869919 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.869919 # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066786 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066786 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071079 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071079 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031526 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.031526 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036064 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.036064 # miss rate for overall accesses
2014-12-02 12:08:25 +01:00
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-07-21 18:19:18 +02:00
system.cpu1.dcache.writebacks::writebacks 5970882 # number of writebacks
system.cpu1.dcache.writebacks::total 5970882 # number of writebacks
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 4768482 # number of replacements
system.cpu1.icache.tags.tagsinuse 496.452247 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 476148096 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 4768994 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 99.842461 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8470205818500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.452247 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969633 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.969633 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-07-21 18:19:18 +02:00
system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
2016-05-31 12:07:18 +02:00
system.cpu1.icache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id
2016-07-21 18:19:18 +02:00
system.cpu1.icache.tags.age_task_id_blocks_1024::2 146 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-07-21 18:19:18 +02:00
system.cpu1.icache.tags.tag_accesses 966603174 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 966603174 # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 476148096 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 476148096 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 476148096 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 476148096 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 476148096 # number of overall hits
system.cpu1.icache.overall_hits::total 476148096 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 4768994 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 4768994 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 4768994 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 4768994 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 4768994 # number of overall misses
system.cpu1.icache.overall_misses::total 4768994 # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst 480917090 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 480917090 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 480917090 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 480917090 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 480917090 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 480917090 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009916 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.009916 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009916 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.009916 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009916 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.009916 # miss rate for overall accesses
2014-10-30 05:50:15 +01:00
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-07-21 18:19:18 +02:00
system.cpu1.icache.writebacks::writebacks 4768482 # number of writebacks
system.cpu1.icache.writebacks::total 4768482 # number of writebacks
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
2016-07-21 18:19:18 +02:00
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 2262891 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 13357.261726 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 14305129 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 2278874 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 6.277279 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 9829187815500 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 13247.067066 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 51.785938 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 58.408722 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.808537 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003161 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003565 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.815263 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 91 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15892 # Occupied blocks per task id
2016-05-31 12:07:18 +02:00
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 53 # Occupied blocks per task id
2016-07-21 18:19:18 +02:00
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1574 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6119 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4359 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3688 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005554 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.969971 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 363588050 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 363588050 # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 348760 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155429 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 504189 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 4050331 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 4050331 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 6688666 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 6688666 # number of WritebackClean hits
2016-05-31 12:07:18 +02:00
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1054 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 1054 # number of UpgradeReq hits
2016-07-21 18:19:18 +02:00
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 613437 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 613437 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4306709 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 4306709 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3087044 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 3087044 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 164780 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 164780 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 348760 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155429 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 4306709 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3700481 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 8511379 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 348760 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155429 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 4306709 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3700481 # number of overall hits
system.cpu1.l2cache.overall_hits::total 8511379 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12218 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9629 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 21847 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 143649 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 143649 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 156474 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 156474 # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 707649 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 707649 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 462285 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 462285 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1220972 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 1220972 # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 268887 # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total 268887 # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12218 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9629 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 462285 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 1928621 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 2412753 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12218 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9629 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 462285 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1928621 # number of overall misses
system.cpu1.l2cache.overall_misses::total 2412753 # number of overall misses
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 360978 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165058 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 526036 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4050331 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 4050331 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 6688666 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 6688666 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 144703 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 144703 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 156474 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 156474 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1321086 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 1321086 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4768994 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 4768994 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4308016 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 4308016 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 433667 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total 433667 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 360978 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165058 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 4768994 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 5629102 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 10924132 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 360978 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165058 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 4768994 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 5629102 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 10924132 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.033847 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.058337 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.041531 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.992716 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.992716 # miss rate for UpgradeReq accesses
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2016-07-21 18:19:18 +02:00
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.535657 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.535657 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.096936 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.096936 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.283419 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.283419 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.620031 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.620031 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.033847 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.058337 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.096936 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.342616 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.220865 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.033847 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.058337 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.096936 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.342616 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.220865 # miss rate for overall accesses
2014-10-30 05:50:15 +01:00
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-07-21 18:19:18 +02:00
system.cpu1.l2cache.writebacks::writebacks 1200117 # number of writebacks
system.cpu1.l2cache.writebacks::total 1200117 # number of writebacks
system.cpu1.toL2Bus.snoop_filter.tot_requests 22145801 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11314039 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 367 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 1748963 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1748793 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 170 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 607661 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 9684671 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 5564 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 5564 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 4050331 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 6689033 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 144703 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 156474 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 301177 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1321086 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1321086 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4768994 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4308016 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 433667 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 433667 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14306730 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18721524 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 366766 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 836674 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 34231694 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 610398984 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 742432303 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1467064 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3346696 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 1357645047 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 5675394 # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic 79399936 # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples 28001988 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.072258 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.258938 # Request fanout histogram
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-07-21 18:19:18 +02:00
system.cpu1.toL2Bus.snoop_fanout::0 25978793 92.77% 92.77% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 2023025 7.22% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 170 0.00% 100.00% # Request fanout histogram
2014-10-30 05:50:15 +01:00
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2015-05-05 09:22:39 +02:00
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-07-21 18:19:18 +02:00
system.cpu1.toL2Bus.snoop_fanout::total 28001988 # Request fanout histogram
system.iobus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
2016-05-31 12:07:18 +02:00
system.iobus.trans_dist::ReadReq 40301 # Transaction distribution
system.iobus.trans_dist::ReadResp 40301 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.iobus.trans_dist::WriteReq 136636 # Transaction distribution
system.iobus.trans_dist::WriteResp 136636 # Transaction distribution
2016-05-31 12:07:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47642 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231218 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231218 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_count::total 353874 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47662 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_size_system.bridge.master::total 155683 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.iobus.pkt_size::total 7496657 # Cumulative packet size per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
2016-05-31 12:07:18 +02:00
system.iocache.tags.replacements 115590 # number of replacements
2016-07-21 18:19:18 +02:00
system.iocache.tags.tagsinuse 11.298808 # Cycle average of tags in use
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2016-05-31 12:07:18 +02:00
system.iocache.tags.sampled_refs 115606 # Sample count of references to valid blocks.
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2016-07-21 18:19:18 +02:00
system.iocache.tags.warmup_cycle 9107772860509 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.845510 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 7.453298 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.240344 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.465831 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.706176 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-05-31 12:07:18 +02:00
system.iocache.tags.tag_accesses 1040838 # Number of tag accesses
system.iocache.tags.data_accesses 1040838 # Number of data accesses
2016-07-21 18:19:18 +02:00
system.iocache.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2016-05-31 12:07:18 +02:00
system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2016-05-31 12:07:18 +02:00
system.iocache.demand_misses::realview.ide 115609 # number of demand (read+write) misses
system.iocache.demand_misses::total 115649 # number of demand (read+write) misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2016-05-31 12:07:18 +02:00
system.iocache.overall_misses::realview.ide 115609 # number of overall misses
system.iocache.overall_misses::total 115649 # number of overall misses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2016-05-31 12:07:18 +02:00
system.iocache.ReadReq_accesses::realview.ide 8881 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8918 # number of ReadReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2016-05-31 12:07:18 +02:00
system.iocache.demand_accesses::realview.ide 115609 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 115649 # number of demand (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2016-05-31 12:07:18 +02:00
system.iocache.overall_accesses::realview.ide 115609 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 115649 # number of overall (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 106694 # number of writebacks
system.iocache.writebacks::total 106694 # number of writebacks
2016-07-21 18:19:18 +02:00
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1774395 # number of replacements
system.l2c.tags.tagsinuse 63409.930559 # Cycle average of tags in use
system.l2c.tags.total_refs 4611925 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1833378 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.515534 # Average number of references to valid blocks.
2016-02-24 10:16:59 +01:00
system.l2c.tags.warmup_cycle 514828500 # Cycle when the warmup percentage was hit.
2016-07-21 18:19:18 +02:00
system.l2c.tags.occ_blocks::writebacks 34658.678488 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 33.446161 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 43.299197 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3299.237288 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 7180.746684 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 272.688902 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 432.688870 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2834.364418 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 14654.780551 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.528849 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000510 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000661 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.050342 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.109569 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004161 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.006602 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.043249 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.223614 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.967559 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 232 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 58751 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 231 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 463 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 3223 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5259 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 49760 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.896469 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 73267769 # Number of tag accesses
system.l2c.tags.data_accesses 73267769 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 2760080 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 2760080 # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data 17858 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 15288 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 33146 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 2554 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 2409 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 4963 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 196672 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 175397 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 372069 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6428 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4634 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 441340 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 728132 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5456 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3654 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 420919 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 680845 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 2291408 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 115975 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 102728 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 218703 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 6428 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 4634 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 441340 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 924804 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 5456 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 3654 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 420919 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 856242 # number of demand (read+write) hits
system.l2c.demand_hits::total 2663477 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 6428 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 4634 # number of overall hits
system.l2c.overall_hits::cpu0.inst 441340 # number of overall hits
system.l2c.overall_hits::cpu0.data 924804 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 5456 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 3654 # number of overall hits
system.l2c.overall_hits::cpu1.inst 420919 # number of overall hits
system.l2c.overall_hits::cpu1.data 856242 # number of overall hits
system.l2c.overall_hits::total 2663477 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 65292 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 60363 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 125655 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 6568 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 6268 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 12836 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 377580 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 423134 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 800714 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2366 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1943 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 57862 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 180178 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3474 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3458 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 41366 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 189464 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 480111 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 478573 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 160244 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 638817 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 2366 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1943 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 57862 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 557758 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 3474 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 3458 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 41366 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 612598 # number of demand (read+write) misses
system.l2c.demand_misses::total 1280825 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 2366 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1943 # number of overall misses
system.l2c.overall_misses::cpu0.inst 57862 # number of overall misses
system.l2c.overall_misses::cpu0.data 557758 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 3474 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 3458 # number of overall misses
system.l2c.overall_misses::cpu1.inst 41366 # number of overall misses
system.l2c.overall_misses::cpu1.data 612598 # number of overall misses
system.l2c.overall_misses::total 1280825 # number of overall misses
system.l2c.WritebackDirty_accesses::writebacks 2760080 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 2760080 # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 83150 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 75651 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 158801 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 9122 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 8677 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 17799 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 574252 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 598531 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 1172783 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8794 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6577 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 499202 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 908310 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8930 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7112 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 462285 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 870309 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 2771519 # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data 594548 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data 262972 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total 857520 # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 8794 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 6577 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 499202 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1482562 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 8930 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 7112 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 462285 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 1468840 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 3944302 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 8794 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 6577 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 499202 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1482562 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 8930 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 7112 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 462285 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 1468840 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 3944302 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.785232 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.797914 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.791273 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.720018 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.722369 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.721164 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.657516 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.706954 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.682747 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.269047 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.295423 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.115909 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.198366 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.389026 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.486220 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.089482 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.217697 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.173230 # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.804936 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.609358 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total 0.744959 # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.269047 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.295423 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.115909 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.376212 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.389026 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.486220 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.089482 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.417062 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.324728 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.269047 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.295423 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.115909 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.376212 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.389026 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.486220 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.089482 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.417062 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.324728 # miss rate for overall accesses
2014-12-02 12:08:25 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-07-21 18:19:18 +02:00
system.l2c.writebacks::writebacks 1478540 # number of writebacks
system.l2c.writebacks::total 1478540 # number of writebacks
system.membus.snoop_filter.tot_requests 4495065 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 2597713 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 3483 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-05-31 12:07:18 +02:00
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-07-21 18:19:18 +02:00
system.membus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 82130 # Transaction distribution
system.membus.trans_dist::ReadResp 571159 # Transaction distribution
system.membus.trans_dist::WriteReq 38798 # Transaction distribution
system.membus.trans_dist::WriteResp 38798 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1585234 # Transaction distribution
system.membus.trans_dist::CleanEvict 247687 # Transaction distribution
system.membus.trans_dist::UpgradeReq 337993 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 306149 # Transaction distribution
system.membus.trans_dist::UpgradeResp 159131 # Transaction distribution
system.membus.trans_dist::ReadExReq 787924 # Transaction distribution
system.membus.trans_dist::ReadExResp 784573 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 489029 # Transaction distribution
system.membus.trans_dist::InvalidateReq 741049 # Transaction distribution
system.membus.trans_dist::InvalidateResp 741049 # Transaction distribution
2016-05-31 12:07:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27542 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6413605 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 6563815 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346888 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 346888 # Packet count per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.membus.pkt_count::total 6910703 # Packet count per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155683 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55084 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 175760092 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 175971063 # Cumulative packet size per connected master and slave (bytes)
2016-05-31 12:07:18 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399168 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7399168 # Cumulative packet size per connected master and slave (bytes)
2016-07-21 18:19:18 +02:00
system.membus.pkt_size::total 183370231 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.membus.snoops 0 # Total snoops (count)
2016-07-21 18:19:18 +02:00
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 4615993 # Request fanout histogram
system.membus.snoop_fanout::mean 0.007281 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.085020 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-07-21 18:19:18 +02:00
system.membus.snoop_fanout::0 4582382 99.27% 99.27% # Request fanout histogram
system.membus.snoop_fanout::1 33611 0.73% 100.00% # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-07-21 18:19:18 +02:00
system.membus.snoop_fanout::total 4615993 # Request fanout histogram
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2016-07-21 18:19:18 +02:00
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2016-07-21 18:19:18 +02:00
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
2014-12-02 12:08:25 +01:00
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
2016-07-21 18:19:18 +02:00
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2016-07-21 18:19:18 +02:00
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-07-21 18:19:18 +02:00
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 11098491 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 5714084 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1638499 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 134977 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 121387 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 13590 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47296281748500 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 82132 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 3539371 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38798 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 38798 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 2760080 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2007636 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 350499 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 311112 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 661611 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 1354403 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 1354403 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 3457239 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 857520 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 857520 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9497179 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8173943 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 17671122 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255360528 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 229634423 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 484994951 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 1809010 # Total snoops (count)
system.toL2Bus.snoopTraffic 94667072 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 13026748 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.284748 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.453600 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-07-21 18:19:18 +02:00
system.toL2Bus.snoop_fanout::0 9330997 71.63% 71.63% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 3682161 28.27% 99.90% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 13590 0.10% 100.00% # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2016-07-21 18:19:18 +02:00
system.toL2Bus.snoop_fanout::total 13026748 # Request fanout histogram
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
